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#define | IFLASH0_SIZE (0x40000u) |
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#define | IFLASH0_PAGE_SIZE (256u) |
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#define | IFLASH0_LOCK_REGION_SIZE (16384u) |
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#define | IFLASH0_NB_OF_PAGES (1024u) |
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#define | IFLASH1_SIZE (0x40000u) |
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#define | IFLASH1_PAGE_SIZE (256u) |
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#define | IFLASH1_LOCK_REGION_SIZE (16384u) |
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#define | IFLASH1_NB_OF_PAGES (1024u) |
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#define | IRAM0_SIZE (0x10000u) |
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#define | IRAM1_SIZE (0x8000u) |
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#define | IFLASH_SIZE (IFLASH0_SIZE+IFLASH1_SIZE) |
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#define | IRAM_SIZE (IRAM0_SIZE+IRAM1_SIZE) |
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#define | IFLASH0_ADDR (0x00080000u) |
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#define | IFLASH1_ADDR (IFLASH0_ADDR+IFLASH0_SIZE) |
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#define | IROM_ADDR (0x00100000u) |
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#define | IRAM0_ADDR (0x20000000u) |
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#define | IRAM1_ADDR (0x20080000u) |
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#define | NFC_RAM_ADDR (0x20100000u) |
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#define | UOTGHS_RAM_ADDR (0x20180000u) |
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#define | EBI_CS0_ADDR (0x60000000u) |
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#define | EBI_CS1_ADDR (0x61000000u) |
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#define | EBI_CS2_ADDR (0x62000000u) |
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#define | EBI_CS3_ADDR (0x63000000u) |
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#define | EBI_CS4_ADDR (0x64000000u) |
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#define | EBI_CS5_ADDR (0x65000000u) |
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#define | EBI_CS6_ADDR (0x66000000u) |
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#define | EBI_CS7_ADDR (0x67000000u) |
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#define | CHIP_FREQ_SLCK_RC_MIN (20000UL) |
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#define | CHIP_FREQ_SLCK_RC (32000UL) |
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#define | CHIP_FREQ_SLCK_RC_MAX (44000UL) |
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#define | CHIP_FREQ_MAINCK_RC_4MHZ (4000000UL) |
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#define | CHIP_FREQ_MAINCK_RC_8MHZ (8000000UL) |
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#define | CHIP_FREQ_MAINCK_RC_12MHZ (12000000UL) |
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#define | CHIP_FREQ_CPU_MAX (84000000UL) |
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#define | CHIP_FREQ_XTAL_32K (32768UL) |
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#define | CHIP_FREQ_XTAL_12M (12000000UL) |
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#define | CHIP_FLASH_WRITE_WAIT_STATE (6U) |
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#define | CHIP_FREQ_FWS_0 (22500000UL) |
| Maximum operating frequency when FWS is 0.
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#define | CHIP_FREQ_FWS_1 (34000000UL) |
| Maximum operating frequency when FWS is 1.
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#define | CHIP_FREQ_FWS_2 (53000000UL) |
| Maximum operating frequency when FWS is 2.
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#define | CHIP_FREQ_FWS_3 (78000000UL) |
| Maximum operating frequency when FWS is 3.
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