Robobo
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Classes | |
struct | Crccu |
Crccu hardware registers. More... | |
Macros | |
#define | CRCCU_DSCR_DSCR_Pos 9 |
#define | CRCCU_DSCR_DSCR_Msk (0x7fffffu << CRCCU_DSCR_DSCR_Pos) |
(CRCCU_DSCR) Descriptor Base Address | |
#define | CRCCU_DSCR_DSCR(value) ((CRCCU_DSCR_DSCR_Msk & ((value) << CRCCU_DSCR_DSCR_Pos))) |
#define | CRCCU_DMA_EN_DMAEN (0x1u << 0) |
(CRCCU_DMA_EN) DMA Enable Register | |
#define | CRCCU_DMA_DIS_DMADIS (0x1u << 0) |
(CRCCU_DMA_DIS) DMA Disable Register | |
#define | CRCCU_DMA_SR_DMASR (0x1u << 0) |
(CRCCU_DMA_SR) DMA Status Register | |
#define | CRCCU_DMA_IER_DMAIER (0x1u << 0) |
(CRCCU_DMA_IER) Interrupt Enable register | |
#define | CRCCU_DMA_IDR_DMAIDR (0x1u << 0) |
(CRCCU_DMA_IDR) Interrupt Disable register | |
#define | CRCCU_DMA_IMR_DMAIMR (0x1u << 0) |
(CRCCU_DMA_IMR) Interrupt Mask Register | |
#define | CRCCU_DMA_ISR_DMAISR (0x1u << 0) |
(CRCCU_DMA_ISR) Interrupt Status register | |
#define | CRCCU_CR_RESET (0x1u << 0) |
(CRCCU_CR) CRC Computation Reset | |
#define | CRCCU_MR_ENABLE (0x1u << 0) |
(CRCCU_MR) CRC Enable | |
#define | CRCCU_MR_COMPARE (0x1u << 1) |
(CRCCU_MR) CRC Compare | |
#define | CRCCU_MR_PTYPE_Pos 2 |
#define | CRCCU_MR_PTYPE_Msk (0x3u << CRCCU_MR_PTYPE_Pos) |
(CRCCU_MR) Primitive Polynomial | |
#define | CRCCU_MR_PTYPE_CCITT8023 (0x0u << 2) |
(CRCCU_MR) Polynom 0x04C11DB7 | |
#define | CRCCU_MR_PTYPE_CASTAGNOLI (0x1u << 2) |
(CRCCU_MR) Polynom 0x1EDC6F41 | |
#define | CRCCU_MR_PTYPE_CCITT16 (0x2u << 2) |
(CRCCU_MR) Polynom 0x1021 | |
#define | CRCCU_MR_DIVIDER_Pos 4 |
#define | CRCCU_MR_DIVIDER_Msk (0xfu << CRCCU_MR_DIVIDER_Pos) |
(CRCCU_MR) Request Divider | |
#define | CRCCU_MR_DIVIDER(value) ((CRCCU_MR_DIVIDER_Msk & ((value) << CRCCU_MR_DIVIDER_Pos))) |
#define | CRCCU_SR_CRC_Pos 0 |
#define | CRCCU_SR_CRC_Msk (0xffffffffu << CRCCU_SR_CRC_Pos) |
(CRCCU_SR) Cyclic Redundancy Check Value | |
#define | CRCCU_IER_ERRIER (0x1u << 0) |
(CRCCU_IER) CRC Error Interrupt Enable | |
#define | CRCCU_IDR_ERRIDR (0x1u << 0) |
(CRCCU_IDR) CRC Error Interrupt Disable | |
#define | CRCCU_IMR_ERRIMR (0x1u << 0) |
(CRCCU_IMR) CRC Error Interrupt Mask | |
#define | CRCCU_ISR_ERRISR (0x1u << 0) |
(CRCCU_ISR) CRC Error Interrupt Status | |
SOFTWARE API DEFINITION FOR Cyclic Redundancy Check Calculation Unit