Pio hardware registers. More...

#include <component_pio.h>

Public Attributes
WoReg	PIO_PER
	(Pio Offset: 0x0000) PIO Enable Register

WoReg	PIO_PDR
	(Pio Offset: 0x0004) PIO Disable Register

RoReg	PIO_PSR
	(Pio Offset: 0x0008) PIO Status Register

RoReg	Reserved1 [1]

WoReg	PIO_OER
	(Pio Offset: 0x0010) Output Enable Register

WoReg	PIO_ODR
	(Pio Offset: 0x0014) Output Disable Register

RoReg	PIO_OSR
	(Pio Offset: 0x0018) Output Status Register

RoReg	Reserved2 [1]

WoReg	PIO_IFER
	(Pio Offset: 0x0020) Glitch Input Filter Enable Register

WoReg	PIO_IFDR
	(Pio Offset: 0x0024) Glitch Input Filter Disable Register

RoReg	PIO_IFSR
	(Pio Offset: 0x0028) Glitch Input Filter Status Register

RoReg	Reserved3 [1]

WoReg	PIO_SODR
	(Pio Offset: 0x0030) Set Output Data Register

WoReg	PIO_CODR
	(Pio Offset: 0x0034) Clear Output Data Register

RwReg	PIO_ODSR
	(Pio Offset: 0x0038) Output Data Status Register

RoReg	PIO_PDSR
	(Pio Offset: 0x003C) Pin Data Status Register

WoReg	PIO_IER
	(Pio Offset: 0x0040) Interrupt Enable Register

WoReg	PIO_IDR
	(Pio Offset: 0x0044) Interrupt Disable Register

RoReg	PIO_IMR
	(Pio Offset: 0x0048) Interrupt Mask Register

RoReg	PIO_ISR
	(Pio Offset: 0x004C) Interrupt Status Register

WoReg	PIO_MDER
	(Pio Offset: 0x0050) Multi-driver Enable Register

WoReg	PIO_MDDR
	(Pio Offset: 0x0054) Multi-driver Disable Register

RoReg	PIO_MDSR
	(Pio Offset: 0x0058) Multi-driver Status Register

RoReg	Reserved4 [1]

WoReg	PIO_PUDR
	(Pio Offset: 0x0060) Pull-up Disable Register

WoReg	PIO_PUER
	(Pio Offset: 0x0064) Pull-up Enable Register

RoReg	PIO_PUSR
	(Pio Offset: 0x0068) Pad Pull-up Status Register

RoReg	Reserved5 [1]

RwReg	PIO_ABCDSR [2]
	(Pio Offset: 0x0070) Peripheral Select Register

RoReg	Reserved6 [2]

WoReg	PIO_IFSCDR
	(Pio Offset: 0x0080) Input Filter Slow Clock Disable Register

WoReg	PIO_IFSCER
	(Pio Offset: 0x0084) Input Filter Slow Clock Enable Register

RoReg	PIO_IFSCSR
	(Pio Offset: 0x0088) Input Filter Slow Clock Status Register

RwReg	PIO_SCDR
	(Pio Offset: 0x008C) Slow Clock Divider Debouncing Register

WoReg	PIO_PPDDR
	(Pio Offset: 0x0090) Pad Pull-down Disable Register

WoReg	PIO_PPDER
	(Pio Offset: 0x0094) Pad Pull-down Enable Register

RoReg	PIO_PPDSR
	(Pio Offset: 0x0098) Pad Pull-down Status Register

RoReg	Reserved7 [1]

WoReg	PIO_OWER
	(Pio Offset: 0x00A0) Output Write Enable

WoReg	PIO_OWDR
	(Pio Offset: 0x00A4) Output Write Disable

RoReg	PIO_OWSR
	(Pio Offset: 0x00A8) Output Write Status Register

RoReg	Reserved8 [1]

WoReg	PIO_AIMER
	(Pio Offset: 0x00B0) Additional Interrupt Modes Enable Register

WoReg	PIO_AIMDR
	(Pio Offset: 0x00B4) Additional Interrupt Modes Disables Register

RoReg	PIO_AIMMR
	(Pio Offset: 0x00B8) Additional Interrupt Modes Mask Register

RoReg	Reserved9 [1]

WoReg	PIO_ESR
	(Pio Offset: 0x00C0) Edge Select Register

WoReg	PIO_LSR
	(Pio Offset: 0x00C4) Level Select Register

RoReg	PIO_ELSR
	(Pio Offset: 0x00C8) Edge/Level Status Register

RoReg	Reserved10 [1]

WoReg	PIO_FELLSR
	(Pio Offset: 0x00D0) Falling Edge/Low Level Select Register

WoReg	PIO_REHLSR
	(Pio Offset: 0x00D4) Rising Edge/ High Level Select Register

RoReg	PIO_FRLHSR
	(Pio Offset: 0x00D8) Fall/Rise - Low/High Status Register

RoReg	Reserved11 [1]

RoReg	PIO_LOCKSR
	(Pio Offset: 0x00E0) Lock Status

RwReg	PIO_WPMR
	(Pio Offset: 0x00E4) Write Protect Mode Register

RoReg	PIO_WPSR
	(Pio Offset: 0x00E8) Write Protect Status Register

RoReg	Reserved12 [5]

RwReg	PIO_SCHMITT
	(Pio Offset: 0x0100) Schmitt Trigger Register

RoReg	Reserved13 [19]

RwReg	PIO_PCMR
	(Pio Offset: 0x150) Parallel Capture Mode Register

WoReg	PIO_PCIER
	(Pio Offset: 0x154) Parallel Capture Interrupt Enable Register

WoReg	PIO_PCIDR
	(Pio Offset: 0x158) Parallel Capture Interrupt Disable Register

RoReg	PIO_PCIMR
	(Pio Offset: 0x15C) Parallel Capture Interrupt Mask Register

RoReg	PIO_PCISR
	(Pio Offset: 0x160) Parallel Capture Interrupt Status Register

RoReg	PIO_PCRHR
	(Pio Offset: 0x164) Parallel Capture Reception Holding Register

RwReg	PIO_RPR
	(Pio Offset: 0x168) Receive Pointer Register

RwReg	PIO_RCR
	(Pio Offset: 0x16C) Receive Counter Register

RoReg	Reserved14 [2]

RwReg	PIO_RNPR
	(Pio Offset: 0x178) Receive Next Pointer Register

RwReg	PIO_RNCR
	(Pio Offset: 0x17C) Receive Next Counter Register

RoReg	Reserved15 [2]

WoReg	PIO_PTCR
	(Pio Offset: 0x188) Transfer Control Register

RoReg	PIO_PTSR
	(Pio Offset: 0x18C) Transfer Status Register

RwReg	PIO_ABSR
	(Pio Offset: 0x0070) Peripheral AB Select Register

WoReg	PIO_SCIFSR
	(Pio Offset: 0x0080) System Clock Glitch Input Filter Select Register

WoReg	PIO_DIFSR
	(Pio Offset: 0x0084) Debouncing Input Filter Select Register

RoReg	PIO_IFDGSR
	(Pio Offset: 0x0088) Glitch or Debouncing Input Filter Clock Selection Status Register

Detailed Description

Pio hardware registers.

The documentation for this struct was generated from the following file:

src/CMSIS/Device/ATMEL/sam3n/include/component/component_pio.h

Public Attributes

Detailed Description