component_pmc.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3U_PMC_COMPONENT_
#define _SAM3U_PMC_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  WoReg PMC_SCER;      
  WoReg PMC_SCDR;      
  RoReg PMC_SCSR;      
  RoReg Reserved1[1];
  WoReg PMC_PCER0;     
  WoReg PMC_PCDR0;     
  RoReg PMC_PCSR0;     
  RwReg CKGR_UCKR;     
  RwReg CKGR_MOR;      
  RoReg CKGR_MCFR;     
  RwReg CKGR_PLLAR;    
  RoReg Reserved2[1];
  RwReg PMC_MCKR;      
  RoReg Reserved3[3];
  RwReg PMC_PCK[3];    
  RoReg Reserved4[5];
  WoReg PMC_IER;       
  WoReg PMC_IDR;       
  RoReg PMC_SR;        
  RoReg PMC_IMR;       
  RwReg PMC_FSMR;      
  RwReg PMC_FSPR;      
  WoReg PMC_FOCR;      
  RoReg Reserved5[26];
  RwReg PMC_WPMR;      
  RoReg PMC_WPSR;      
} Pmc;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- PMC_SCER : (PMC Offset: 0x0000) System Clock Enable Register -------- */
#define PMC_SCER_PCK0 (0x1u << 8) 
#define PMC_SCER_PCK1 (0x1u << 9) 
#define PMC_SCER_PCK2 (0x1u << 10) 
/* -------- PMC_SCDR : (PMC Offset: 0x0004) System Clock Disable Register -------- */
#define PMC_SCDR_PCK0 (0x1u << 8) 
#define PMC_SCDR_PCK1 (0x1u << 9) 
#define PMC_SCDR_PCK2 (0x1u << 10) 
/* -------- PMC_SCSR : (PMC Offset: 0x0008) System Clock Status Register -------- */
#define PMC_SCSR_PCK0 (0x1u << 8) 
#define PMC_SCSR_PCK1 (0x1u << 9) 
#define PMC_SCSR_PCK2 (0x1u << 10) 
/* -------- PMC_PCER0 : (PMC Offset: 0x0010) Peripheral Clock Enable Register 0 -------- */
#define PMC_PCER0_PID2 (0x1u << 2) 
#define PMC_PCER0_PID3 (0x1u << 3) 
#define PMC_PCER0_PID4 (0x1u << 4) 
#define PMC_PCER0_PID5 (0x1u << 5) 
#define PMC_PCER0_PID6 (0x1u << 6) 
#define PMC_PCER0_PID7 (0x1u << 7) 
#define PMC_PCER0_PID8 (0x1u << 8) 
#define PMC_PCER0_PID9 (0x1u << 9) 
#define PMC_PCER0_PID10 (0x1u << 10) 
#define PMC_PCER0_PID11 (0x1u << 11) 
#define PMC_PCER0_PID12 (0x1u << 12) 
#define PMC_PCER0_PID13 (0x1u << 13) 
#define PMC_PCER0_PID14 (0x1u << 14) 
#define PMC_PCER0_PID15 (0x1u << 15) 
#define PMC_PCER0_PID16 (0x1u << 16) 
#define PMC_PCER0_PID18 (0x1u << 18) 
#define PMC_PCER0_PID19 (0x1u << 19) 
#define PMC_PCER0_PID20 (0x1u << 20) 
#define PMC_PCER0_PID21 (0x1u << 21) 
#define PMC_PCER0_PID22 (0x1u << 22) 
#define PMC_PCER0_PID23 (0x1u << 23) 
#define PMC_PCER0_PID24 (0x1u << 24) 
#define PMC_PCER0_PID25 (0x1u << 25) 
#define PMC_PCER0_PID26 (0x1u << 26) 
#define PMC_PCER0_PID27 (0x1u << 27) 
#define PMC_PCER0_PID28 (0x1u << 28) 
#define PMC_PCER0_PID29 (0x1u << 29) 
/* -------- PMC_PCDR0 : (PMC Offset: 0x0014) Peripheral Clock Disable Register 0 -------- */
#define PMC_PCDR0_PID2 (0x1u << 2) 
#define PMC_PCDR0_PID3 (0x1u << 3) 
#define PMC_PCDR0_PID4 (0x1u << 4) 
#define PMC_PCDR0_PID5 (0x1u << 5) 
#define PMC_PCDR0_PID6 (0x1u << 6) 
#define PMC_PCDR0_PID7 (0x1u << 7) 
#define PMC_PCDR0_PID8 (0x1u << 8) 
#define PMC_PCDR0_PID9 (0x1u << 9) 
#define PMC_PCDR0_PID10 (0x1u << 10) 
#define PMC_PCDR0_PID11 (0x1u << 11) 
#define PMC_PCDR0_PID12 (0x1u << 12) 
#define PMC_PCDR0_PID13 (0x1u << 13) 
#define PMC_PCDR0_PID14 (0x1u << 14) 
#define PMC_PCDR0_PID15 (0x1u << 15) 
#define PMC_PCDR0_PID16 (0x1u << 16) 
#define PMC_PCDR0_PID18 (0x1u << 18) 
#define PMC_PCDR0_PID19 (0x1u << 19) 
#define PMC_PCDR0_PID20 (0x1u << 20) 
#define PMC_PCDR0_PID21 (0x1u << 21) 
#define PMC_PCDR0_PID22 (0x1u << 22) 
#define PMC_PCDR0_PID23 (0x1u << 23) 
#define PMC_PCDR0_PID24 (0x1u << 24) 
#define PMC_PCDR0_PID25 (0x1u << 25) 
#define PMC_PCDR0_PID26 (0x1u << 26) 
#define PMC_PCDR0_PID27 (0x1u << 27) 
#define PMC_PCDR0_PID28 (0x1u << 28) 
#define PMC_PCDR0_PID29 (0x1u << 29) 
/* -------- PMC_PCSR0 : (PMC Offset: 0x0018) Peripheral Clock Status Register 0 -------- */
#define PMC_PCSR0_PID2 (0x1u << 2) 
#define PMC_PCSR0_PID3 (0x1u << 3) 
#define PMC_PCSR0_PID4 (0x1u << 4) 
#define PMC_PCSR0_PID5 (0x1u << 5) 
#define PMC_PCSR0_PID6 (0x1u << 6) 
#define PMC_PCSR0_PID7 (0x1u << 7) 
#define PMC_PCSR0_PID8 (0x1u << 8) 
#define PMC_PCSR0_PID9 (0x1u << 9) 
#define PMC_PCSR0_PID10 (0x1u << 10) 
#define PMC_PCSR0_PID11 (0x1u << 11) 
#define PMC_PCSR0_PID12 (0x1u << 12) 
#define PMC_PCSR0_PID13 (0x1u << 13) 
#define PMC_PCSR0_PID14 (0x1u << 14) 
#define PMC_PCSR0_PID15 (0x1u << 15) 
#define PMC_PCSR0_PID16 (0x1u << 16) 
#define PMC_PCSR0_PID18 (0x1u << 18) 
#define PMC_PCSR0_PID19 (0x1u << 19) 
#define PMC_PCSR0_PID20 (0x1u << 20) 
#define PMC_PCSR0_PID21 (0x1u << 21) 
#define PMC_PCSR0_PID22 (0x1u << 22) 
#define PMC_PCSR0_PID23 (0x1u << 23) 
#define PMC_PCSR0_PID24 (0x1u << 24) 
#define PMC_PCSR0_PID25 (0x1u << 25) 
#define PMC_PCSR0_PID26 (0x1u << 26) 
#define PMC_PCSR0_PID27 (0x1u << 27) 
#define PMC_PCSR0_PID28 (0x1u << 28) 
#define PMC_PCSR0_PID29 (0x1u << 29) 
/* -------- CKGR_UCKR : (PMC Offset: 0x001C) UTMI Clock Register -------- */
#define CKGR_UCKR_UPLLEN (0x1u << 16) 
#define CKGR_UCKR_UPLLCOUNT_Pos 20
#define CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) 
#define CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos)))
/* -------- CKGR_MOR : (PMC Offset: 0x0020) Main Oscillator Register -------- */
#define CKGR_MOR_MOSCXTEN (0x1u << 0) 
#define CKGR_MOR_MOSCXTBY (0x1u << 1) 
#define CKGR_MOR_MOSCRCEN (0x1u << 3) 
#define CKGR_MOR_MOSCRCF_Pos 4
#define CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) 
#define   CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) 
#define   CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) 
#define   CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) 
#define CKGR_MOR_MOSCXTST_Pos 8
#define CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) 
#define CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos)))
#define CKGR_MOR_KEY_Pos 16
#define CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) 
#define CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos)))
#define CKGR_MOR_MOSCSEL (0x1u << 24) 
#define CKGR_MOR_CFDEN (0x1u << 25) 
/* -------- CKGR_MCFR : (PMC Offset: 0x0024) Main Clock Frequency Register -------- */
#define CKGR_MCFR_MAINF_Pos 0
#define CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) 
#define CKGR_MCFR_MAINFRDY (0x1u << 16) 
/* -------- CKGR_PLLAR : (PMC Offset: 0x0028) PLLA Register -------- */
#define CKGR_PLLAR_DIVA_Pos 0
#define CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) 
#define CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos)))
#define CKGR_PLLAR_PLLACOUNT_Pos 8
#define CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) 
#define CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos)))
#define CKGR_PLLAR_MULA_Pos 16
#define CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) 
#define CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos)))
#define CKGR_PLLAR_ONE (0x1u << 29) 
/* -------- PMC_MCKR : (PMC Offset: 0x0030) Master Clock Register -------- */
#define PMC_MCKR_CSS_Pos 0
#define PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) 
#define   PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) 
#define   PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) 
#define   PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) 
#define   PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) 
#define PMC_MCKR_PRES_Pos 4
#define PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) 
#define   PMC_MCKR_PRES_CLK_1 (0x0u << 4) 
#define   PMC_MCKR_PRES_CLK_2 (0x1u << 4) 
#define   PMC_MCKR_PRES_CLK_4 (0x2u << 4) 
#define   PMC_MCKR_PRES_CLK_8 (0x3u << 4) 
#define   PMC_MCKR_PRES_CLK_16 (0x4u << 4) 
#define   PMC_MCKR_PRES_CLK_32 (0x5u << 4) 
#define   PMC_MCKR_PRES_CLK_64 (0x6u << 4) 
#define   PMC_MCKR_PRES_CLK_3 (0x7u << 4) 
#define PMC_MCKR_PLLADIV2 (0x1u << 12) 
#define PMC_MCKR_UPLLDIV2 (0x1u << 13) 
/* -------- PMC_PCK[3] : (PMC Offset: 0x0040) Programmable Clock 0 Register -------- */
#define PMC_PCK_CSS_Pos 0
#define PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) 
#define   PMC_PCK_CSS_SLOW_CLK (0x0u << 0) 
#define   PMC_PCK_CSS_MAIN_CLK (0x1u << 0) 
#define   PMC_PCK_CSS_PLLA_CLK (0x2u << 0) 
#define   PMC_PCK_CSS_UPLL_CLK (0x3u << 0) 
#define   PMC_PCK_CSS_MCK (0x4u << 0) 
#define PMC_PCK_PRES_Pos 4
#define PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) 
#define   PMC_PCK_PRES_CLK_1 (0x0u << 4) 
#define   PMC_PCK_PRES_CLK_2 (0x1u << 4) 
#define   PMC_PCK_PRES_CLK_4 (0x2u << 4) 
#define   PMC_PCK_PRES_CLK_8 (0x3u << 4) 
#define   PMC_PCK_PRES_CLK_16 (0x4u << 4) 
#define   PMC_PCK_PRES_CLK_32 (0x5u << 4) 
#define   PMC_PCK_PRES_CLK_64 (0x6u << 4) 
/* -------- PMC_IER : (PMC Offset: 0x0060) Interrupt Enable Register -------- */
#define PMC_IER_MOSCXTS (0x1u << 0) 
#define PMC_IER_LOCKA (0x1u << 1) 
#define PMC_IER_MCKRDY (0x1u << 3) 
#define PMC_IER_LOCKU (0x1u << 6) 
#define PMC_IER_PCKRDY0 (0x1u << 8) 
#define PMC_IER_PCKRDY1 (0x1u << 9) 
#define PMC_IER_PCKRDY2 (0x1u << 10) 
#define PMC_IER_MOSCSELS (0x1u << 16) 
#define PMC_IER_MOSCRCS (0x1u << 17) 
#define PMC_IER_CFDEV (0x1u << 18) 
/* -------- PMC_IDR : (PMC Offset: 0x0064) Interrupt Disable Register -------- */
#define PMC_IDR_MOSCXTS (0x1u << 0) 
#define PMC_IDR_LOCKA (0x1u << 1) 
#define PMC_IDR_MCKRDY (0x1u << 3) 
#define PMC_IDR_LOCKU (0x1u << 6) 
#define PMC_IDR_PCKRDY0 (0x1u << 8) 
#define PMC_IDR_PCKRDY1 (0x1u << 9) 
#define PMC_IDR_PCKRDY2 (0x1u << 10) 
#define PMC_IDR_MOSCSELS (0x1u << 16) 
#define PMC_IDR_MOSCRCS (0x1u << 17) 
#define PMC_IDR_CFDEV (0x1u << 18) 
/* -------- PMC_SR : (PMC Offset: 0x0068) Status Register -------- */
#define PMC_SR_MOSCXTS (0x1u << 0) 
#define PMC_SR_LOCKA (0x1u << 1) 
#define PMC_SR_MCKRDY (0x1u << 3) 
#define PMC_SR_LOCKU (0x1u << 6) 
#define PMC_SR_OSCSELS (0x1u << 7) 
#define PMC_SR_PCKRDY0 (0x1u << 8) 
#define PMC_SR_PCKRDY1 (0x1u << 9) 
#define PMC_SR_PCKRDY2 (0x1u << 10) 
#define PMC_SR_MOSCSELS (0x1u << 16) 
#define PMC_SR_MOSCRCS (0x1u << 17) 
#define PMC_SR_CFDEV (0x1u << 18) 
#define PMC_SR_CFDS (0x1u << 19) 
#define PMC_SR_FOS (0x1u << 20) 
/* -------- PMC_IMR : (PMC Offset: 0x006C) Interrupt Mask Register -------- */
#define PMC_IMR_MOSCXTS (0x1u << 0) 
#define PMC_IMR_LOCKA (0x1u << 1) 
#define PMC_IMR_MCKRDY (0x1u << 3) 
#define PMC_IMR_LOCKU (0x1u << 6) 
#define PMC_IMR_PCKRDY0 (0x1u << 8) 
#define PMC_IMR_PCKRDY1 (0x1u << 9) 
#define PMC_IMR_PCKRDY2 (0x1u << 10) 
#define PMC_IMR_MOSCSELS (0x1u << 16) 
#define PMC_IMR_MOSCRCS (0x1u << 17) 
#define PMC_IMR_CFDEV (0x1u << 18) 
/* -------- PMC_FSMR : (PMC Offset: 0x0070) Fast Startup Mode Register -------- */
#define PMC_FSMR_FSTT0 (0x1u << 0) 
#define PMC_FSMR_FSTT1 (0x1u << 1) 
#define PMC_FSMR_FSTT2 (0x1u << 2) 
#define PMC_FSMR_FSTT3 (0x1u << 3) 
#define PMC_FSMR_FSTT4 (0x1u << 4) 
#define PMC_FSMR_FSTT5 (0x1u << 5) 
#define PMC_FSMR_FSTT6 (0x1u << 6) 
#define PMC_FSMR_FSTT7 (0x1u << 7) 
#define PMC_FSMR_FSTT8 (0x1u << 8) 
#define PMC_FSMR_FSTT9 (0x1u << 9) 
#define PMC_FSMR_FSTT10 (0x1u << 10) 
#define PMC_FSMR_FSTT11 (0x1u << 11) 
#define PMC_FSMR_FSTT12 (0x1u << 12) 
#define PMC_FSMR_FSTT13 (0x1u << 13) 
#define PMC_FSMR_FSTT14 (0x1u << 14) 
#define PMC_FSMR_FSTT15 (0x1u << 15) 
#define PMC_FSMR_RTTAL (0x1u << 16) 
#define PMC_FSMR_RTCAL (0x1u << 17) 
#define PMC_FSMR_USBAL (0x1u << 18) 
#define PMC_FSMR_LPM (0x1u << 20) 
/* -------- PMC_FSPR : (PMC Offset: 0x0074) Fast Startup Polarity Register -------- */
#define PMC_FSPR_FSTP0 (0x1u << 0) 
#define PMC_FSPR_FSTP1 (0x1u << 1) 
#define PMC_FSPR_FSTP2 (0x1u << 2) 
#define PMC_FSPR_FSTP3 (0x1u << 3) 
#define PMC_FSPR_FSTP4 (0x1u << 4) 
#define PMC_FSPR_FSTP5 (0x1u << 5) 
#define PMC_FSPR_FSTP6 (0x1u << 6) 
#define PMC_FSPR_FSTP7 (0x1u << 7) 
#define PMC_FSPR_FSTP8 (0x1u << 8) 
#define PMC_FSPR_FSTP9 (0x1u << 9) 
#define PMC_FSPR_FSTP10 (0x1u << 10) 
#define PMC_FSPR_FSTP11 (0x1u << 11) 
#define PMC_FSPR_FSTP12 (0x1u << 12) 
#define PMC_FSPR_FSTP13 (0x1u << 13) 
#define PMC_FSPR_FSTP14 (0x1u << 14) 
#define PMC_FSPR_FSTP15 (0x1u << 15) 
/* -------- PMC_FOCR : (PMC Offset: 0x0078) Fault Output Clear Register -------- */
#define PMC_FOCR_FOCLR (0x1u << 0) 
/* -------- PMC_WPMR : (PMC Offset: 0x00E4) Write Protect Mode Register -------- */
#define PMC_WPMR_WPEN (0x1u << 0) 
#define PMC_WPMR_WPKEY_Pos 8
#define PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) 
#define PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos)))
/* -------- PMC_WPSR : (PMC Offset: 0x00E8) Write Protect Status Register -------- */
#define PMC_WPSR_WPVS (0x1u << 0) 
#define PMC_WPSR_WPVSRC_Pos 8
#define PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) 


#endif /* _SAM3U_PMC_COMPONENT_ */