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#define | PMC_SCER_PCK0 (0x1u << 8) |
| | (PMC_SCER) Programmable Clock 0 Output Enable
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#define | PMC_SCER_PCK1 (0x1u << 9) |
| | (PMC_SCER) Programmable Clock 1 Output Enable
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#define | PMC_SCER_PCK2 (0x1u << 10) |
| | (PMC_SCER) Programmable Clock 2 Output Enable
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#define | PMC_SCDR_PCK0 (0x1u << 8) |
| | (PMC_SCDR) Programmable Clock 0 Output Disable
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#define | PMC_SCDR_PCK1 (0x1u << 9) |
| | (PMC_SCDR) Programmable Clock 1 Output Disable
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#define | PMC_SCDR_PCK2 (0x1u << 10) |
| | (PMC_SCDR) Programmable Clock 2 Output Disable
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#define | PMC_SCSR_PCK0 (0x1u << 8) |
| | (PMC_SCSR) Programmable Clock 0 Output Status
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#define | PMC_SCSR_PCK1 (0x1u << 9) |
| | (PMC_SCSR) Programmable Clock 1 Output Status
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#define | PMC_SCSR_PCK2 (0x1u << 10) |
| | (PMC_SCSR) Programmable Clock 2 Output Status
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#define | PMC_PCER0_PID2 (0x1u << 2) |
| | (PMC_PCER0) Peripheral Clock 2 Enable
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#define | PMC_PCER0_PID3 (0x1u << 3) |
| | (PMC_PCER0) Peripheral Clock 3 Enable
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#define | PMC_PCER0_PID4 (0x1u << 4) |
| | (PMC_PCER0) Peripheral Clock 4 Enable
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#define | PMC_PCER0_PID5 (0x1u << 5) |
| | (PMC_PCER0) Peripheral Clock 5 Enable
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#define | PMC_PCER0_PID6 (0x1u << 6) |
| | (PMC_PCER0) Peripheral Clock 6 Enable
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#define | PMC_PCER0_PID7 (0x1u << 7) |
| | (PMC_PCER0) Peripheral Clock 7 Enable
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#define | PMC_PCER0_PID8 (0x1u << 8) |
| | (PMC_PCER0) Peripheral Clock 8 Enable
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#define | PMC_PCER0_PID9 (0x1u << 9) |
| | (PMC_PCER0) Peripheral Clock 9 Enable
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#define | PMC_PCER0_PID10 (0x1u << 10) |
| | (PMC_PCER0) Peripheral Clock 10 Enable
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#define | PMC_PCER0_PID11 (0x1u << 11) |
| | (PMC_PCER0) Peripheral Clock 11 Enable
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#define | PMC_PCER0_PID12 (0x1u << 12) |
| | (PMC_PCER0) Peripheral Clock 12 Enable
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#define | PMC_PCER0_PID13 (0x1u << 13) |
| | (PMC_PCER0) Peripheral Clock 13 Enable
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#define | PMC_PCER0_PID14 (0x1u << 14) |
| | (PMC_PCER0) Peripheral Clock 14 Enable
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#define | PMC_PCER0_PID15 (0x1u << 15) |
| | (PMC_PCER0) Peripheral Clock 15 Enable
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#define | PMC_PCER0_PID16 (0x1u << 16) |
| | (PMC_PCER0) Peripheral Clock 16 Enable
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#define | PMC_PCER0_PID18 (0x1u << 18) |
| | (PMC_PCER0) Peripheral Clock 18 Enable
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#define | PMC_PCER0_PID19 (0x1u << 19) |
| | (PMC_PCER0) Peripheral Clock 19 Enable
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#define | PMC_PCER0_PID20 (0x1u << 20) |
| | (PMC_PCER0) Peripheral Clock 20 Enable
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#define | PMC_PCER0_PID21 (0x1u << 21) |
| | (PMC_PCER0) Peripheral Clock 21 Enable
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#define | PMC_PCER0_PID22 (0x1u << 22) |
| | (PMC_PCER0) Peripheral Clock 22 Enable
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#define | PMC_PCER0_PID23 (0x1u << 23) |
| | (PMC_PCER0) Peripheral Clock 23 Enable
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#define | PMC_PCER0_PID24 (0x1u << 24) |
| | (PMC_PCER0) Peripheral Clock 24 Enable
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#define | PMC_PCER0_PID25 (0x1u << 25) |
| | (PMC_PCER0) Peripheral Clock 25 Enable
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#define | PMC_PCER0_PID26 (0x1u << 26) |
| | (PMC_PCER0) Peripheral Clock 26 Enable
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#define | PMC_PCER0_PID27 (0x1u << 27) |
| | (PMC_PCER0) Peripheral Clock 27 Enable
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#define | PMC_PCER0_PID28 (0x1u << 28) |
| | (PMC_PCER0) Peripheral Clock 28 Enable
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#define | PMC_PCER0_PID29 (0x1u << 29) |
| | (PMC_PCER0) Peripheral Clock 29 Enable
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#define | PMC_PCDR0_PID2 (0x1u << 2) |
| | (PMC_PCDR0) Peripheral Clock 2 Disable
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#define | PMC_PCDR0_PID3 (0x1u << 3) |
| | (PMC_PCDR0) Peripheral Clock 3 Disable
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#define | PMC_PCDR0_PID4 (0x1u << 4) |
| | (PMC_PCDR0) Peripheral Clock 4 Disable
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#define | PMC_PCDR0_PID5 (0x1u << 5) |
| | (PMC_PCDR0) Peripheral Clock 5 Disable
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#define | PMC_PCDR0_PID6 (0x1u << 6) |
| | (PMC_PCDR0) Peripheral Clock 6 Disable
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#define | PMC_PCDR0_PID7 (0x1u << 7) |
| | (PMC_PCDR0) Peripheral Clock 7 Disable
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#define | PMC_PCDR0_PID8 (0x1u << 8) |
| | (PMC_PCDR0) Peripheral Clock 8 Disable
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#define | PMC_PCDR0_PID9 (0x1u << 9) |
| | (PMC_PCDR0) Peripheral Clock 9 Disable
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#define | PMC_PCDR0_PID10 (0x1u << 10) |
| | (PMC_PCDR0) Peripheral Clock 10 Disable
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#define | PMC_PCDR0_PID11 (0x1u << 11) |
| | (PMC_PCDR0) Peripheral Clock 11 Disable
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#define | PMC_PCDR0_PID12 (0x1u << 12) |
| | (PMC_PCDR0) Peripheral Clock 12 Disable
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#define | PMC_PCDR0_PID13 (0x1u << 13) |
| | (PMC_PCDR0) Peripheral Clock 13 Disable
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#define | PMC_PCDR0_PID14 (0x1u << 14) |
| | (PMC_PCDR0) Peripheral Clock 14 Disable
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#define | PMC_PCDR0_PID15 (0x1u << 15) |
| | (PMC_PCDR0) Peripheral Clock 15 Disable
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#define | PMC_PCDR0_PID16 (0x1u << 16) |
| | (PMC_PCDR0) Peripheral Clock 16 Disable
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#define | PMC_PCDR0_PID18 (0x1u << 18) |
| | (PMC_PCDR0) Peripheral Clock 18 Disable
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#define | PMC_PCDR0_PID19 (0x1u << 19) |
| | (PMC_PCDR0) Peripheral Clock 19 Disable
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#define | PMC_PCDR0_PID20 (0x1u << 20) |
| | (PMC_PCDR0) Peripheral Clock 20 Disable
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#define | PMC_PCDR0_PID21 (0x1u << 21) |
| | (PMC_PCDR0) Peripheral Clock 21 Disable
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#define | PMC_PCDR0_PID22 (0x1u << 22) |
| | (PMC_PCDR0) Peripheral Clock 22 Disable
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#define | PMC_PCDR0_PID23 (0x1u << 23) |
| | (PMC_PCDR0) Peripheral Clock 23 Disable
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#define | PMC_PCDR0_PID24 (0x1u << 24) |
| | (PMC_PCDR0) Peripheral Clock 24 Disable
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#define | PMC_PCDR0_PID25 (0x1u << 25) |
| | (PMC_PCDR0) Peripheral Clock 25 Disable
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#define | PMC_PCDR0_PID26 (0x1u << 26) |
| | (PMC_PCDR0) Peripheral Clock 26 Disable
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#define | PMC_PCDR0_PID27 (0x1u << 27) |
| | (PMC_PCDR0) Peripheral Clock 27 Disable
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#define | PMC_PCDR0_PID28 (0x1u << 28) |
| | (PMC_PCDR0) Peripheral Clock 28 Disable
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#define | PMC_PCDR0_PID29 (0x1u << 29) |
| | (PMC_PCDR0) Peripheral Clock 29 Disable
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#define | PMC_PCSR0_PID2 (0x1u << 2) |
| | (PMC_PCSR0) Peripheral Clock 2 Status
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#define | PMC_PCSR0_PID3 (0x1u << 3) |
| | (PMC_PCSR0) Peripheral Clock 3 Status
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#define | PMC_PCSR0_PID4 (0x1u << 4) |
| | (PMC_PCSR0) Peripheral Clock 4 Status
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#define | PMC_PCSR0_PID5 (0x1u << 5) |
| | (PMC_PCSR0) Peripheral Clock 5 Status
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#define | PMC_PCSR0_PID6 (0x1u << 6) |
| | (PMC_PCSR0) Peripheral Clock 6 Status
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#define | PMC_PCSR0_PID7 (0x1u << 7) |
| | (PMC_PCSR0) Peripheral Clock 7 Status
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#define | PMC_PCSR0_PID8 (0x1u << 8) |
| | (PMC_PCSR0) Peripheral Clock 8 Status
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#define | PMC_PCSR0_PID9 (0x1u << 9) |
| | (PMC_PCSR0) Peripheral Clock 9 Status
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#define | PMC_PCSR0_PID10 (0x1u << 10) |
| | (PMC_PCSR0) Peripheral Clock 10 Status
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#define | PMC_PCSR0_PID11 (0x1u << 11) |
| | (PMC_PCSR0) Peripheral Clock 11 Status
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#define | PMC_PCSR0_PID12 (0x1u << 12) |
| | (PMC_PCSR0) Peripheral Clock 12 Status
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#define | PMC_PCSR0_PID13 (0x1u << 13) |
| | (PMC_PCSR0) Peripheral Clock 13 Status
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#define | PMC_PCSR0_PID14 (0x1u << 14) |
| | (PMC_PCSR0) Peripheral Clock 14 Status
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#define | PMC_PCSR0_PID15 (0x1u << 15) |
| | (PMC_PCSR0) Peripheral Clock 15 Status
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#define | PMC_PCSR0_PID16 (0x1u << 16) |
| | (PMC_PCSR0) Peripheral Clock 16 Status
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#define | PMC_PCSR0_PID18 (0x1u << 18) |
| | (PMC_PCSR0) Peripheral Clock 18 Status
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#define | PMC_PCSR0_PID19 (0x1u << 19) |
| | (PMC_PCSR0) Peripheral Clock 19 Status
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#define | PMC_PCSR0_PID20 (0x1u << 20) |
| | (PMC_PCSR0) Peripheral Clock 20 Status
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#define | PMC_PCSR0_PID21 (0x1u << 21) |
| | (PMC_PCSR0) Peripheral Clock 21 Status
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#define | PMC_PCSR0_PID22 (0x1u << 22) |
| | (PMC_PCSR0) Peripheral Clock 22 Status
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#define | PMC_PCSR0_PID23 (0x1u << 23) |
| | (PMC_PCSR0) Peripheral Clock 23 Status
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#define | PMC_PCSR0_PID24 (0x1u << 24) |
| | (PMC_PCSR0) Peripheral Clock 24 Status
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#define | PMC_PCSR0_PID25 (0x1u << 25) |
| | (PMC_PCSR0) Peripheral Clock 25 Status
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#define | PMC_PCSR0_PID26 (0x1u << 26) |
| | (PMC_PCSR0) Peripheral Clock 26 Status
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#define | PMC_PCSR0_PID27 (0x1u << 27) |
| | (PMC_PCSR0) Peripheral Clock 27 Status
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#define | PMC_PCSR0_PID28 (0x1u << 28) |
| | (PMC_PCSR0) Peripheral Clock 28 Status
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#define | PMC_PCSR0_PID29 (0x1u << 29) |
| | (PMC_PCSR0) Peripheral Clock 29 Status
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#define | CKGR_UCKR_UPLLEN (0x1u << 16) |
| | (CKGR_UCKR) UTMI PLL Enable
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#define | CKGR_UCKR_UPLLCOUNT_Pos 20 |
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#define | CKGR_UCKR_UPLLCOUNT_Msk (0xfu << CKGR_UCKR_UPLLCOUNT_Pos) |
| | (CKGR_UCKR) UTMI PLL Start-up Time
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#define | CKGR_UCKR_UPLLCOUNT(value) ((CKGR_UCKR_UPLLCOUNT_Msk & ((value) << CKGR_UCKR_UPLLCOUNT_Pos))) |
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#define | CKGR_MOR_MOSCXTEN (0x1u << 0) |
| | (CKGR_MOR) Main Crystal Oscillator Enable
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#define | CKGR_MOR_MOSCXTBY (0x1u << 1) |
| | (CKGR_MOR) Main Crystal Oscillator Bypass
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#define | CKGR_MOR_MOSCRCEN (0x1u << 3) |
| | (CKGR_MOR) Main On-Chip RC Oscillator Enable
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#define | CKGR_MOR_MOSCRCF_Pos 4 |
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#define | CKGR_MOR_MOSCRCF_Msk (0x7u << CKGR_MOR_MOSCRCF_Pos) |
| | (CKGR_MOR) Main On-Chip RC Oscillator Frequency Selection
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#define | CKGR_MOR_MOSCRCF_4_MHz (0x0u << 4) |
| | (CKGR_MOR) The Fast RC Oscillator Frequency is at 4 MHz (default)
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#define | CKGR_MOR_MOSCRCF_8_MHz (0x1u << 4) |
| | (CKGR_MOR) The Fast RC Oscillator Frequency is at 8 MHz
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#define | CKGR_MOR_MOSCRCF_12_MHz (0x2u << 4) |
| | (CKGR_MOR) The Fast RC Oscillator Frequency is at 12 MHz
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#define | CKGR_MOR_MOSCXTST_Pos 8 |
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#define | CKGR_MOR_MOSCXTST_Msk (0xffu << CKGR_MOR_MOSCXTST_Pos) |
| | (CKGR_MOR) Main Crystal Oscillator Start-up Time
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#define | CKGR_MOR_MOSCXTST(value) ((CKGR_MOR_MOSCXTST_Msk & ((value) << CKGR_MOR_MOSCXTST_Pos))) |
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#define | CKGR_MOR_KEY_Pos 16 |
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#define | CKGR_MOR_KEY_Msk (0xffu << CKGR_MOR_KEY_Pos) |
| | (CKGR_MOR) Password
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#define | CKGR_MOR_KEY(value) ((CKGR_MOR_KEY_Msk & ((value) << CKGR_MOR_KEY_Pos))) |
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#define | CKGR_MOR_MOSCSEL (0x1u << 24) |
| | (CKGR_MOR) Main Oscillator Selection
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#define | CKGR_MOR_CFDEN (0x1u << 25) |
| | (CKGR_MOR) Clock Failure Detector Enable
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#define | CKGR_MCFR_MAINF_Pos 0 |
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#define | CKGR_MCFR_MAINF_Msk (0xffffu << CKGR_MCFR_MAINF_Pos) |
| | (CKGR_MCFR) Main Clock Frequency
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#define | CKGR_MCFR_MAINFRDY (0x1u << 16) |
| | (CKGR_MCFR) Main Clock Ready
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#define | CKGR_PLLAR_DIVA_Pos 0 |
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#define | CKGR_PLLAR_DIVA_Msk (0xffu << CKGR_PLLAR_DIVA_Pos) |
| | (CKGR_PLLAR) Divider
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#define | CKGR_PLLAR_DIVA(value) ((CKGR_PLLAR_DIVA_Msk & ((value) << CKGR_PLLAR_DIVA_Pos))) |
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#define | CKGR_PLLAR_PLLACOUNT_Pos 8 |
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#define | CKGR_PLLAR_PLLACOUNT_Msk (0x3fu << CKGR_PLLAR_PLLACOUNT_Pos) |
| | (CKGR_PLLAR) PLLA Counter
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#define | CKGR_PLLAR_PLLACOUNT(value) ((CKGR_PLLAR_PLLACOUNT_Msk & ((value) << CKGR_PLLAR_PLLACOUNT_Pos))) |
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#define | CKGR_PLLAR_MULA_Pos 16 |
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#define | CKGR_PLLAR_MULA_Msk (0x7ffu << CKGR_PLLAR_MULA_Pos) |
| | (CKGR_PLLAR) PLLA Multiplier
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#define | CKGR_PLLAR_MULA(value) ((CKGR_PLLAR_MULA_Msk & ((value) << CKGR_PLLAR_MULA_Pos))) |
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#define | CKGR_PLLAR_ONE (0x1u << 29) |
| | (CKGR_PLLAR) Must Be Set to 1
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#define | PMC_MCKR_CSS_Pos 0 |
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#define | PMC_MCKR_CSS_Msk (0x3u << PMC_MCKR_CSS_Pos) |
| | (PMC_MCKR) Master Clock Source Selection
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#define | PMC_MCKR_CSS_SLOW_CLK (0x0u << 0) |
| | (PMC_MCKR) Slow Clock is selected
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#define | PMC_MCKR_CSS_MAIN_CLK (0x1u << 0) |
| | (PMC_MCKR) Main Clock is selected
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#define | PMC_MCKR_CSS_PLLA_CLK (0x2u << 0) |
| | (PMC_MCKR) PLLA Clock is selected
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#define | PMC_MCKR_CSS_UPLL_CLK (0x3u << 0) |
| | (PMC_MCKR) UPLLClock is selected
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#define | PMC_MCKR_PRES_Pos 4 |
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#define | PMC_MCKR_PRES_Msk (0x7u << PMC_MCKR_PRES_Pos) |
| | (PMC_MCKR) Processor Clock Prescaler
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#define | PMC_MCKR_PRES_CLK_1 (0x0u << 4) |
| | (PMC_MCKR) Selected clock
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#define | PMC_MCKR_PRES_CLK_2 (0x1u << 4) |
| | (PMC_MCKR) Selected clock divided by 2
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#define | PMC_MCKR_PRES_CLK_4 (0x2u << 4) |
| | (PMC_MCKR) Selected clock divided by 4
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#define | PMC_MCKR_PRES_CLK_8 (0x3u << 4) |
| | (PMC_MCKR) Selected clock divided by 8
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#define | PMC_MCKR_PRES_CLK_16 (0x4u << 4) |
| | (PMC_MCKR) Selected clock divided by 16
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#define | PMC_MCKR_PRES_CLK_32 (0x5u << 4) |
| | (PMC_MCKR) Selected clock divided by 32
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#define | PMC_MCKR_PRES_CLK_64 (0x6u << 4) |
| | (PMC_MCKR) Selected clock divided by 64
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#define | PMC_MCKR_PRES_CLK_3 (0x7u << 4) |
| | (PMC_MCKR) Selected clock divided by 3
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#define | PMC_MCKR_PLLADIV2 (0x1u << 12) |
| | (PMC_MCKR) PLLA Divisor by 2
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#define | PMC_MCKR_UPLLDIV2 (0x1u << 13) |
| | (PMC_MCKR) UPLL Divisor by 2
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#define | PMC_PCK_CSS_Pos 0 |
| |
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#define | PMC_PCK_CSS_Msk (0x7u << PMC_PCK_CSS_Pos) |
| | (PMC_PCK[3]) Master Clock Source Selection
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#define | PMC_PCK_CSS_SLOW_CLK (0x0u << 0) |
| | (PMC_PCK[3]) Slow Clock is selected
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#define | PMC_PCK_CSS_MAIN_CLK (0x1u << 0) |
| | (PMC_PCK[3]) Main Clock is selected
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#define | PMC_PCK_CSS_PLLA_CLK (0x2u << 0) |
| | (PMC_PCK[3]) PLLA Clock is selected
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#define | PMC_PCK_CSS_UPLL_CLK (0x3u << 0) |
| | (PMC_PCK[3]) UPLL Clock is selected
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#define | PMC_PCK_CSS_MCK (0x4u << 0) |
| | (PMC_PCK[3]) Master Clock is selected
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#define | PMC_PCK_PRES_Pos 4 |
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#define | PMC_PCK_PRES_Msk (0x7u << PMC_PCK_PRES_Pos) |
| | (PMC_PCK[3]) Programmable Clock Prescaler
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#define | PMC_PCK_PRES_CLK_1 (0x0u << 4) |
| | (PMC_PCK[3]) Selected clock
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#define | PMC_PCK_PRES_CLK_2 (0x1u << 4) |
| | (PMC_PCK[3]) Selected clock divided by 2
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#define | PMC_PCK_PRES_CLK_4 (0x2u << 4) |
| | (PMC_PCK[3]) Selected clock divided by 4
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#define | PMC_PCK_PRES_CLK_8 (0x3u << 4) |
| | (PMC_PCK[3]) Selected clock divided by 8
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#define | PMC_PCK_PRES_CLK_16 (0x4u << 4) |
| | (PMC_PCK[3]) Selected clock divided by 16
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#define | PMC_PCK_PRES_CLK_32 (0x5u << 4) |
| | (PMC_PCK[3]) Selected clock divided by 32
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#define | PMC_PCK_PRES_CLK_64 (0x6u << 4) |
| | (PMC_PCK[3]) Selected clock divided by 64
|
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#define | PMC_IER_MOSCXTS (0x1u << 0) |
| | (PMC_IER) Main Crystal Oscillator Status Interrupt Enable
|
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#define | PMC_IER_LOCKA (0x1u << 1) |
| | (PMC_IER) PLLA Lock Interrupt Enable
|
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#define | PMC_IER_MCKRDY (0x1u << 3) |
| | (PMC_IER) Master Clock Ready Interrupt Enable
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#define | PMC_IER_LOCKU (0x1u << 6) |
| | (PMC_IER) UTMI PLL Lock Interrupt Enable
|
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#define | PMC_IER_PCKRDY0 (0x1u << 8) |
| | (PMC_IER) Programmable Clock Ready 0 Interrupt Enable
|
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#define | PMC_IER_PCKRDY1 (0x1u << 9) |
| | (PMC_IER) Programmable Clock Ready 1 Interrupt Enable
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#define | PMC_IER_PCKRDY2 (0x1u << 10) |
| | (PMC_IER) Programmable Clock Ready 2 Interrupt Enable
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#define | PMC_IER_MOSCSELS (0x1u << 16) |
| | (PMC_IER) Main Oscillator Selection Status Interrupt Enable
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#define | PMC_IER_MOSCRCS (0x1u << 17) |
| | (PMC_IER) Main On-Chip RC Status Interrupt Enable
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#define | PMC_IER_CFDEV (0x1u << 18) |
| | (PMC_IER) Clock Failure Detector Event Interrupt Enable
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#define | PMC_IDR_MOSCXTS (0x1u << 0) |
| | (PMC_IDR) Main Crystal Oscillator Status Interrupt Disable
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#define | PMC_IDR_LOCKA (0x1u << 1) |
| | (PMC_IDR) PLLA Lock Interrupt Disable
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#define | PMC_IDR_MCKRDY (0x1u << 3) |
| | (PMC_IDR) Master Clock Ready Interrupt Disable
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#define | PMC_IDR_LOCKU (0x1u << 6) |
| | (PMC_IDR) UTMI PLL Lock Interrupt Disable
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#define | PMC_IDR_PCKRDY0 (0x1u << 8) |
| | (PMC_IDR) Programmable Clock Ready 0 Interrupt Disable
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#define | PMC_IDR_PCKRDY1 (0x1u << 9) |
| | (PMC_IDR) Programmable Clock Ready 1 Interrupt Disable
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#define | PMC_IDR_PCKRDY2 (0x1u << 10) |
| | (PMC_IDR) Programmable Clock Ready 2 Interrupt Disable
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#define | PMC_IDR_MOSCSELS (0x1u << 16) |
| | (PMC_IDR) Main Oscillator Selection Status Interrupt Disable
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#define | PMC_IDR_MOSCRCS (0x1u << 17) |
| | (PMC_IDR) Main On-Chip RC Status Interrupt Disable
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#define | PMC_IDR_CFDEV (0x1u << 18) |
| | (PMC_IDR) Clock Failure Detector Event Interrupt Disable
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#define | PMC_SR_MOSCXTS (0x1u << 0) |
| | (PMC_SR) Main XTAL Oscillator Status
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#define | PMC_SR_LOCKA (0x1u << 1) |
| | (PMC_SR) PLLA Lock Status
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#define | PMC_SR_MCKRDY (0x1u << 3) |
| | (PMC_SR) Master Clock Status
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#define | PMC_SR_LOCKU (0x1u << 6) |
| | (PMC_SR) UTMI PLL Lock Status
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#define | PMC_SR_OSCSELS (0x1u << 7) |
| | (PMC_SR) Slow Clock Oscillator Selection
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#define | PMC_SR_PCKRDY0 (0x1u << 8) |
| | (PMC_SR) Programmable Clock Ready Status
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#define | PMC_SR_PCKRDY1 (0x1u << 9) |
| | (PMC_SR) Programmable Clock Ready Status
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#define | PMC_SR_PCKRDY2 (0x1u << 10) |
| | (PMC_SR) Programmable Clock Ready Status
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#define | PMC_SR_MOSCSELS (0x1u << 16) |
| | (PMC_SR) Main Oscillator Selection Status
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#define | PMC_SR_MOSCRCS (0x1u << 17) |
| | (PMC_SR) Main On-Chip RC Oscillator Status
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#define | PMC_SR_CFDEV (0x1u << 18) |
| | (PMC_SR) Clock Failure Detector Event
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#define | PMC_SR_CFDS (0x1u << 19) |
| | (PMC_SR) Clock Failure Detector Status
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#define | PMC_SR_FOS (0x1u << 20) |
| | (PMC_SR) Clock Failure Detector Fault Output Status
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#define | PMC_IMR_MOSCXTS (0x1u << 0) |
| | (PMC_IMR) Main Crystal Oscillator Status Interrupt Mask
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#define | PMC_IMR_LOCKA (0x1u << 1) |
| | (PMC_IMR) PLLA Lock Interrupt Mask
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#define | PMC_IMR_MCKRDY (0x1u << 3) |
| | (PMC_IMR) Master Clock Ready Interrupt Mask
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#define | PMC_IMR_LOCKU (0x1u << 6) |
| | (PMC_IMR) UTMI PLL Lock Interrupt Mask
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#define | PMC_IMR_PCKRDY0 (0x1u << 8) |
| | (PMC_IMR) Programmable Clock Ready 0 Interrupt Mask
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#define | PMC_IMR_PCKRDY1 (0x1u << 9) |
| | (PMC_IMR) Programmable Clock Ready 1 Interrupt Mask
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#define | PMC_IMR_PCKRDY2 (0x1u << 10) |
| | (PMC_IMR) Programmable Clock Ready 2 Interrupt Mask
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#define | PMC_IMR_MOSCSELS (0x1u << 16) |
| | (PMC_IMR) Main Oscillator Selection Status Interrupt Mask
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#define | PMC_IMR_MOSCRCS (0x1u << 17) |
| | (PMC_IMR) Main On-Chip RC Status Interrupt Mask
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#define | PMC_IMR_CFDEV (0x1u << 18) |
| | (PMC_IMR) Clock Failure Detector Event Interrupt Mask
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#define | PMC_FSMR_FSTT0 (0x1u << 0) |
| | (PMC_FSMR) Fast Startup Input Enable 0
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#define | PMC_FSMR_FSTT1 (0x1u << 1) |
| | (PMC_FSMR) Fast Startup Input Enable 1
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#define | PMC_FSMR_FSTT2 (0x1u << 2) |
| | (PMC_FSMR) Fast Startup Input Enable 2
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#define | PMC_FSMR_FSTT3 (0x1u << 3) |
| | (PMC_FSMR) Fast Startup Input Enable 3
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#define | PMC_FSMR_FSTT4 (0x1u << 4) |
| | (PMC_FSMR) Fast Startup Input Enable 4
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#define | PMC_FSMR_FSTT5 (0x1u << 5) |
| | (PMC_FSMR) Fast Startup Input Enable 5
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#define | PMC_FSMR_FSTT6 (0x1u << 6) |
| | (PMC_FSMR) Fast Startup Input Enable 6
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#define | PMC_FSMR_FSTT7 (0x1u << 7) |
| | (PMC_FSMR) Fast Startup Input Enable 7
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#define | PMC_FSMR_FSTT8 (0x1u << 8) |
| | (PMC_FSMR) Fast Startup Input Enable 8
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#define | PMC_FSMR_FSTT9 (0x1u << 9) |
| | (PMC_FSMR) Fast Startup Input Enable 9
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#define | PMC_FSMR_FSTT10 (0x1u << 10) |
| | (PMC_FSMR) Fast Startup Input Enable 10
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#define | PMC_FSMR_FSTT11 (0x1u << 11) |
| | (PMC_FSMR) Fast Startup Input Enable 11
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#define | PMC_FSMR_FSTT12 (0x1u << 12) |
| | (PMC_FSMR) Fast Startup Input Enable 12
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#define | PMC_FSMR_FSTT13 (0x1u << 13) |
| | (PMC_FSMR) Fast Startup Input Enable 13
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#define | PMC_FSMR_FSTT14 (0x1u << 14) |
| | (PMC_FSMR) Fast Startup Input Enable 14
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#define | PMC_FSMR_FSTT15 (0x1u << 15) |
| | (PMC_FSMR) Fast Startup Input Enable 15
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#define | PMC_FSMR_RTTAL (0x1u << 16) |
| | (PMC_FSMR) RTT Alarm Enable
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#define | PMC_FSMR_RTCAL (0x1u << 17) |
| | (PMC_FSMR) RTC Alarm Enable
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#define | PMC_FSMR_USBAL (0x1u << 18) |
| | (PMC_FSMR) USB Alarm Enable
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#define | PMC_FSMR_LPM (0x1u << 20) |
| | (PMC_FSMR) Low Power Mode
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#define | PMC_FSPR_FSTP0 (0x1u << 0) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP1 (0x1u << 1) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP2 (0x1u << 2) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP3 (0x1u << 3) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP4 (0x1u << 4) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP5 (0x1u << 5) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP6 (0x1u << 6) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP7 (0x1u << 7) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP8 (0x1u << 8) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP9 (0x1u << 9) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP10 (0x1u << 10) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP11 (0x1u << 11) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP12 (0x1u << 12) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP13 (0x1u << 13) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP14 (0x1u << 14) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FSPR_FSTP15 (0x1u << 15) |
| | (PMC_FSPR) Fast Startup Input Polarityx
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#define | PMC_FOCR_FOCLR (0x1u << 0) |
| | (PMC_FOCR) Fault Output Clear
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#define | PMC_WPMR_WPEN (0x1u << 0) |
| | (PMC_WPMR) Write Protect Enable
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#define | PMC_WPMR_WPKEY_Pos 8 |
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#define | PMC_WPMR_WPKEY_Msk (0xffffffu << PMC_WPMR_WPKEY_Pos) |
| | (PMC_WPMR) Write Protect KEY
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#define | PMC_WPMR_WPKEY(value) ((PMC_WPMR_WPKEY_Msk & ((value) << PMC_WPMR_WPKEY_Pos))) |
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#define | PMC_WPSR_WPVS (0x1u << 0) |
| | (PMC_WPSR) Write Protect Violation Status
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#define | PMC_WPSR_WPVSRC_Pos 8 |
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#define | PMC_WPSR_WPVSRC_Msk (0xffffu << PMC_WPSR_WPVSRC_Pos) |
| | (PMC_WPSR) Write Protect Violation Source
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1.8.11 
