Robobo
component_uart.h
1 /* ----------------------------------------------------------------------------
2  * SAM Software Package License
3  * ----------------------------------------------------------------------------
4  * Copyright (c) 2012, Atmel Corporation
5  *
6  * All rights reserved.
7  *
8  * Redistribution and use in source and binary forms, with or without
9  * modification, are permitted provided that the following condition is met:
10  *
11  * - Redistributions of source code must retain the above copyright notice,
12  * this list of conditions and the disclaimer below.
13  *
14  * Atmel's name may not be used to endorse or promote products derived from
15  * this software without specific prior written permission.
16  *
17  * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
18  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
19  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
20  * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
21  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
23  * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
24  * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
25  * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
26  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27  * ----------------------------------------------------------------------------
28  */
29 
30 #ifndef _SAM3S8_UART_COMPONENT_
31 #define _SAM3S8_UART_COMPONENT_
32 
33 /* ============================================================================= */
35 /* ============================================================================= */
38 
39 #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))
40 
41 typedef struct {
42  WoReg UART_CR;
43  RwReg UART_MR;
44  WoReg UART_IER;
45  WoReg UART_IDR;
46  RoReg UART_IMR;
47  RoReg UART_SR;
48  RoReg UART_RHR;
49  WoReg UART_THR;
50  RwReg UART_BRGR;
51  RoReg Reserved1[55];
52  RwReg UART_RPR;
53  RwReg UART_RCR;
54  RwReg UART_TPR;
55  RwReg UART_TCR;
56  RwReg UART_RNPR;
57  RwReg UART_RNCR;
58  RwReg UART_TNPR;
59  RwReg UART_TNCR;
60  WoReg UART_PTCR;
61  RoReg UART_PTSR;
62 } Uart;
63 #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
64 /* -------- UART_CR : (UART Offset: 0x0000) Control Register -------- */
65 #define UART_CR_RSTRX (0x1u << 2)
66 #define UART_CR_RSTTX (0x1u << 3)
67 #define UART_CR_RXEN (0x1u << 4)
68 #define UART_CR_RXDIS (0x1u << 5)
69 #define UART_CR_TXEN (0x1u << 6)
70 #define UART_CR_TXDIS (0x1u << 7)
71 #define UART_CR_RSTSTA (0x1u << 8)
72 /* -------- UART_MR : (UART Offset: 0x0004) Mode Register -------- */
73 #define UART_MR_PAR_Pos 9
74 #define UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos)
75 #define UART_MR_PAR_EVEN (0x0u << 9)
76 #define UART_MR_PAR_ODD (0x1u << 9)
77 #define UART_MR_PAR_SPACE (0x2u << 9)
78 #define UART_MR_PAR_MARK (0x3u << 9)
79 #define UART_MR_PAR_NO (0x4u << 9)
80 #define UART_MR_CHMODE_Pos 14
81 #define UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos)
82 #define UART_MR_CHMODE_NORMAL (0x0u << 14)
83 #define UART_MR_CHMODE_AUTOMATIC (0x1u << 14)
84 #define UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14)
85 #define UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14)
86 /* -------- UART_IER : (UART Offset: 0x0008) Interrupt Enable Register -------- */
87 #define UART_IER_RXRDY (0x1u << 0)
88 #define UART_IER_TXRDY (0x1u << 1)
89 #define UART_IER_ENDRX (0x1u << 3)
90 #define UART_IER_ENDTX (0x1u << 4)
91 #define UART_IER_OVRE (0x1u << 5)
92 #define UART_IER_FRAME (0x1u << 6)
93 #define UART_IER_PARE (0x1u << 7)
94 #define UART_IER_TXEMPTY (0x1u << 9)
95 #define UART_IER_TXBUFE (0x1u << 11)
96 #define UART_IER_RXBUFF (0x1u << 12)
97 /* -------- UART_IDR : (UART Offset: 0x000C) Interrupt Disable Register -------- */
98 #define UART_IDR_RXRDY (0x1u << 0)
99 #define UART_IDR_TXRDY (0x1u << 1)
100 #define UART_IDR_ENDRX (0x1u << 3)
101 #define UART_IDR_ENDTX (0x1u << 4)
102 #define UART_IDR_OVRE (0x1u << 5)
103 #define UART_IDR_FRAME (0x1u << 6)
104 #define UART_IDR_PARE (0x1u << 7)
105 #define UART_IDR_TXEMPTY (0x1u << 9)
106 #define UART_IDR_TXBUFE (0x1u << 11)
107 #define UART_IDR_RXBUFF (0x1u << 12)
108 /* -------- UART_IMR : (UART Offset: 0x0010) Interrupt Mask Register -------- */
109 #define UART_IMR_RXRDY (0x1u << 0)
110 #define UART_IMR_TXRDY (0x1u << 1)
111 #define UART_IMR_ENDRX (0x1u << 3)
112 #define UART_IMR_ENDTX (0x1u << 4)
113 #define UART_IMR_OVRE (0x1u << 5)
114 #define UART_IMR_FRAME (0x1u << 6)
115 #define UART_IMR_PARE (0x1u << 7)
116 #define UART_IMR_TXEMPTY (0x1u << 9)
117 #define UART_IMR_TXBUFE (0x1u << 11)
118 #define UART_IMR_RXBUFF (0x1u << 12)
119 /* -------- UART_SR : (UART Offset: 0x0014) Status Register -------- */
120 #define UART_SR_RXRDY (0x1u << 0)
121 #define UART_SR_TXRDY (0x1u << 1)
122 #define UART_SR_ENDRX (0x1u << 3)
123 #define UART_SR_ENDTX (0x1u << 4)
124 #define UART_SR_OVRE (0x1u << 5)
125 #define UART_SR_FRAME (0x1u << 6)
126 #define UART_SR_PARE (0x1u << 7)
127 #define UART_SR_TXEMPTY (0x1u << 9)
128 #define UART_SR_TXBUFE (0x1u << 11)
129 #define UART_SR_RXBUFF (0x1u << 12)
130 /* -------- UART_RHR : (UART Offset: 0x0018) Receive Holding Register -------- */
131 #define UART_RHR_RXCHR_Pos 0
132 #define UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos)
133 /* -------- UART_THR : (UART Offset: 0x001C) Transmit Holding Register -------- */
134 #define UART_THR_TXCHR_Pos 0
135 #define UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos)
136 #define UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos)))
137 /* -------- UART_BRGR : (UART Offset: 0x0020) Baud Rate Generator Register -------- */
138 #define UART_BRGR_CD_Pos 0
139 #define UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos)
140 #define UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos)))
141 /* -------- UART_RPR : (UART Offset: 0x100) Receive Pointer Register -------- */
142 #define UART_RPR_RXPTR_Pos 0
143 #define UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos)
144 #define UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos)))
145 /* -------- UART_RCR : (UART Offset: 0x104) Receive Counter Register -------- */
146 #define UART_RCR_RXCTR_Pos 0
147 #define UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos)
148 #define UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos)))
149 /* -------- UART_TPR : (UART Offset: 0x108) Transmit Pointer Register -------- */
150 #define UART_TPR_TXPTR_Pos 0
151 #define UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos)
152 #define UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos)))
153 /* -------- UART_TCR : (UART Offset: 0x10C) Transmit Counter Register -------- */
154 #define UART_TCR_TXCTR_Pos 0
155 #define UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos)
156 #define UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos)))
157 /* -------- UART_RNPR : (UART Offset: 0x110) Receive Next Pointer Register -------- */
158 #define UART_RNPR_RXNPTR_Pos 0
159 #define UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos)
160 #define UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos)))
161 /* -------- UART_RNCR : (UART Offset: 0x114) Receive Next Counter Register -------- */
162 #define UART_RNCR_RXNCTR_Pos 0
163 #define UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos)
164 #define UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos)))
165 /* -------- UART_TNPR : (UART Offset: 0x118) Transmit Next Pointer Register -------- */
166 #define UART_TNPR_TXNPTR_Pos 0
167 #define UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos)
168 #define UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos)))
169 /* -------- UART_TNCR : (UART Offset: 0x11C) Transmit Next Counter Register -------- */
170 #define UART_TNCR_TXNCTR_Pos 0
171 #define UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos)
172 #define UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos)))
173 /* -------- UART_PTCR : (UART Offset: 0x120) Transfer Control Register -------- */
174 #define UART_PTCR_RXTEN (0x1u << 0)
175 #define UART_PTCR_RXTDIS (0x1u << 1)
176 #define UART_PTCR_TXTEN (0x1u << 8)
177 #define UART_PTCR_TXTDIS (0x1u << 9)
178 /* -------- UART_PTSR : (UART Offset: 0x124) Transfer Status Register -------- */
179 #define UART_PTSR_RXTEN (0x1u << 0)
180 #define UART_PTSR_TXTEN (0x1u << 8)
183 
184 
185 #endif /* _SAM3S8_UART_COMPONENT_ */
RwReg
volatile uint32_t RwReg
Definition: sam3n00a.h:54
WoReg
volatile uint32_t WoReg
Definition: sam3n00a.h:53
RoReg
volatile const uint32_t RoReg
Definition: sam3n00a.h:49
Uart
Uart hardware registers.
Definition: component_uart.h:41