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#define | UART_CR_RSTRX (0x1u << 2) |
| | (UART_CR) Reset Receiver
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#define | UART_CR_RSTTX (0x1u << 3) |
| | (UART_CR) Reset Transmitter
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#define | UART_CR_RXEN (0x1u << 4) |
| | (UART_CR) Receiver Enable
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#define | UART_CR_RXDIS (0x1u << 5) |
| | (UART_CR) Receiver Disable
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#define | UART_CR_TXEN (0x1u << 6) |
| | (UART_CR) Transmitter Enable
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#define | UART_CR_TXDIS (0x1u << 7) |
| | (UART_CR) Transmitter Disable
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#define | UART_CR_RSTSTA (0x1u << 8) |
| | (UART_CR) Reset Status Bits
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#define | UART_MR_PAR_Pos 9 |
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#define | UART_MR_PAR_Msk (0x7u << UART_MR_PAR_Pos) |
| | (UART_MR) Parity Type
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#define | UART_MR_PAR_EVEN (0x0u << 9) |
| | (UART_MR) Even parity
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#define | UART_MR_PAR_ODD (0x1u << 9) |
| | (UART_MR) Odd parity
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#define | UART_MR_PAR_SPACE (0x2u << 9) |
| | (UART_MR) Space: parity forced to 0
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#define | UART_MR_PAR_MARK (0x3u << 9) |
| | (UART_MR) Mark: parity forced to 1
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#define | UART_MR_PAR_NO (0x4u << 9) |
| | (UART_MR) No parity
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#define | UART_MR_CHMODE_Pos 14 |
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#define | UART_MR_CHMODE_Msk (0x3u << UART_MR_CHMODE_Pos) |
| | (UART_MR) Channel Mode
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#define | UART_MR_CHMODE_NORMAL (0x0u << 14) |
| | (UART_MR) Normal Mode
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#define | UART_MR_CHMODE_AUTOMATIC (0x1u << 14) |
| | (UART_MR) Automatic Echo
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#define | UART_MR_CHMODE_LOCAL_LOOPBACK (0x2u << 14) |
| | (UART_MR) Local Loopback
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#define | UART_MR_CHMODE_REMOTE_LOOPBACK (0x3u << 14) |
| | (UART_MR) Remote Loopback
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#define | UART_IER_RXRDY (0x1u << 0) |
| | (UART_IER) Enable RXRDY Interrupt
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#define | UART_IER_TXRDY (0x1u << 1) |
| | (UART_IER) Enable TXRDY Interrupt
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#define | UART_IER_ENDRX (0x1u << 3) |
| | (UART_IER) Enable End of Receive Transfer Interrupt
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#define | UART_IER_ENDTX (0x1u << 4) |
| | (UART_IER) Enable End of Transmit Interrupt
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#define | UART_IER_OVRE (0x1u << 5) |
| | (UART_IER) Enable Overrun Error Interrupt
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#define | UART_IER_FRAME (0x1u << 6) |
| | (UART_IER) Enable Framing Error Interrupt
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#define | UART_IER_PARE (0x1u << 7) |
| | (UART_IER) Enable Parity Error Interrupt
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#define | UART_IER_TXEMPTY (0x1u << 9) |
| | (UART_IER) Enable TXEMPTY Interrupt
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#define | UART_IER_TXBUFE (0x1u << 11) |
| | (UART_IER) Enable Buffer Empty Interrupt
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#define | UART_IER_RXBUFF (0x1u << 12) |
| | (UART_IER) Enable Buffer Full Interrupt
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#define | UART_IDR_RXRDY (0x1u << 0) |
| | (UART_IDR) Disable RXRDY Interrupt
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#define | UART_IDR_TXRDY (0x1u << 1) |
| | (UART_IDR) Disable TXRDY Interrupt
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#define | UART_IDR_ENDRX (0x1u << 3) |
| | (UART_IDR) Disable End of Receive Transfer Interrupt
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#define | UART_IDR_ENDTX (0x1u << 4) |
| | (UART_IDR) Disable End of Transmit Interrupt
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#define | UART_IDR_OVRE (0x1u << 5) |
| | (UART_IDR) Disable Overrun Error Interrupt
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#define | UART_IDR_FRAME (0x1u << 6) |
| | (UART_IDR) Disable Framing Error Interrupt
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#define | UART_IDR_PARE (0x1u << 7) |
| | (UART_IDR) Disable Parity Error Interrupt
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#define | UART_IDR_TXEMPTY (0x1u << 9) |
| | (UART_IDR) Disable TXEMPTY Interrupt
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#define | UART_IDR_TXBUFE (0x1u << 11) |
| | (UART_IDR) Disable Buffer Empty Interrupt
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#define | UART_IDR_RXBUFF (0x1u << 12) |
| | (UART_IDR) Disable Buffer Full Interrupt
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#define | UART_IMR_RXRDY (0x1u << 0) |
| | (UART_IMR) Mask RXRDY Interrupt
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#define | UART_IMR_TXRDY (0x1u << 1) |
| | (UART_IMR) Disable TXRDY Interrupt
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#define | UART_IMR_ENDRX (0x1u << 3) |
| | (UART_IMR) Mask End of Receive Transfer Interrupt
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#define | UART_IMR_ENDTX (0x1u << 4) |
| | (UART_IMR) Mask End of Transmit Interrupt
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#define | UART_IMR_OVRE (0x1u << 5) |
| | (UART_IMR) Mask Overrun Error Interrupt
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#define | UART_IMR_FRAME (0x1u << 6) |
| | (UART_IMR) Mask Framing Error Interrupt
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#define | UART_IMR_PARE (0x1u << 7) |
| | (UART_IMR) Mask Parity Error Interrupt
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#define | UART_IMR_TXEMPTY (0x1u << 9) |
| | (UART_IMR) Mask TXEMPTY Interrupt
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#define | UART_IMR_TXBUFE (0x1u << 11) |
| | (UART_IMR) Mask TXBUFE Interrupt
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#define | UART_IMR_RXBUFF (0x1u << 12) |
| | (UART_IMR) Mask RXBUFF Interrupt
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#define | UART_SR_RXRDY (0x1u << 0) |
| | (UART_SR) Receiver Ready
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#define | UART_SR_TXRDY (0x1u << 1) |
| | (UART_SR) Transmitter Ready
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#define | UART_SR_ENDRX (0x1u << 3) |
| | (UART_SR) End of Receiver Transfer
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#define | UART_SR_ENDTX (0x1u << 4) |
| | (UART_SR) End of Transmitter Transfer
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#define | UART_SR_OVRE (0x1u << 5) |
| | (UART_SR) Overrun Error
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#define | UART_SR_FRAME (0x1u << 6) |
| | (UART_SR) Framing Error
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#define | UART_SR_PARE (0x1u << 7) |
| | (UART_SR) Parity Error
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#define | UART_SR_TXEMPTY (0x1u << 9) |
| | (UART_SR) Transmitter Empty
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#define | UART_SR_TXBUFE (0x1u << 11) |
| | (UART_SR) Transmission Buffer Empty
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#define | UART_SR_RXBUFF (0x1u << 12) |
| | (UART_SR) Receive Buffer Full
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#define | UART_RHR_RXCHR_Pos 0 |
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#define | UART_RHR_RXCHR_Msk (0xffu << UART_RHR_RXCHR_Pos) |
| | (UART_RHR) Received Character
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#define | UART_THR_TXCHR_Pos 0 |
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#define | UART_THR_TXCHR_Msk (0xffu << UART_THR_TXCHR_Pos) |
| | (UART_THR) Character to be Transmitted
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#define | UART_THR_TXCHR(value) ((UART_THR_TXCHR_Msk & ((value) << UART_THR_TXCHR_Pos))) |
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#define | UART_BRGR_CD_Pos 0 |
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#define | UART_BRGR_CD_Msk (0xffffu << UART_BRGR_CD_Pos) |
| | (UART_BRGR) Clock Divisor
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#define | UART_BRGR_CD(value) ((UART_BRGR_CD_Msk & ((value) << UART_BRGR_CD_Pos))) |
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#define | UART_RPR_RXPTR_Pos 0 |
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#define | UART_RPR_RXPTR_Msk (0xffffffffu << UART_RPR_RXPTR_Pos) |
| | (UART_RPR) Receive Pointer Register
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#define | UART_RPR_RXPTR(value) ((UART_RPR_RXPTR_Msk & ((value) << UART_RPR_RXPTR_Pos))) |
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#define | UART_RCR_RXCTR_Pos 0 |
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#define | UART_RCR_RXCTR_Msk (0xffffu << UART_RCR_RXCTR_Pos) |
| | (UART_RCR) Receive Counter Register
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#define | UART_RCR_RXCTR(value) ((UART_RCR_RXCTR_Msk & ((value) << UART_RCR_RXCTR_Pos))) |
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#define | UART_TPR_TXPTR_Pos 0 |
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#define | UART_TPR_TXPTR_Msk (0xffffffffu << UART_TPR_TXPTR_Pos) |
| | (UART_TPR) Transmit Counter Register
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#define | UART_TPR_TXPTR(value) ((UART_TPR_TXPTR_Msk & ((value) << UART_TPR_TXPTR_Pos))) |
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#define | UART_TCR_TXCTR_Pos 0 |
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#define | UART_TCR_TXCTR_Msk (0xffffu << UART_TCR_TXCTR_Pos) |
| | (UART_TCR) Transmit Counter Register
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#define | UART_TCR_TXCTR(value) ((UART_TCR_TXCTR_Msk & ((value) << UART_TCR_TXCTR_Pos))) |
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#define | UART_RNPR_RXNPTR_Pos 0 |
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#define | UART_RNPR_RXNPTR_Msk (0xffffffffu << UART_RNPR_RXNPTR_Pos) |
| | (UART_RNPR) Receive Next Pointer
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#define | UART_RNPR_RXNPTR(value) ((UART_RNPR_RXNPTR_Msk & ((value) << UART_RNPR_RXNPTR_Pos))) |
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#define | UART_RNCR_RXNCTR_Pos 0 |
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#define | UART_RNCR_RXNCTR_Msk (0xffffu << UART_RNCR_RXNCTR_Pos) |
| | (UART_RNCR) Receive Next Counter
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#define | UART_RNCR_RXNCTR(value) ((UART_RNCR_RXNCTR_Msk & ((value) << UART_RNCR_RXNCTR_Pos))) |
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#define | UART_TNPR_TXNPTR_Pos 0 |
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#define | UART_TNPR_TXNPTR_Msk (0xffffffffu << UART_TNPR_TXNPTR_Pos) |
| | (UART_TNPR) Transmit Next Pointer
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#define | UART_TNPR_TXNPTR(value) ((UART_TNPR_TXNPTR_Msk & ((value) << UART_TNPR_TXNPTR_Pos))) |
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#define | UART_TNCR_TXNCTR_Pos 0 |
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#define | UART_TNCR_TXNCTR_Msk (0xffffu << UART_TNCR_TXNCTR_Pos) |
| | (UART_TNCR) Transmit Counter Next
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#define | UART_TNCR_TXNCTR(value) ((UART_TNCR_TXNCTR_Msk & ((value) << UART_TNCR_TXNCTR_Pos))) |
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#define | UART_PTCR_RXTEN (0x1u << 0) |
| | (UART_PTCR) Receiver Transfer Enable
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#define | UART_PTCR_RXTDIS (0x1u << 1) |
| | (UART_PTCR) Receiver Transfer Disable
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#define | UART_PTCR_TXTEN (0x1u << 8) |
| | (UART_PTCR) Transmitter Transfer Enable
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#define | UART_PTCR_TXTDIS (0x1u << 9) |
| | (UART_PTCR) Transmitter Transfer Disable
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#define | UART_PTSR_RXTEN (0x1u << 0) |
| | (UART_PTSR) Receiver Transfer Enable
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#define | UART_PTSR_TXTEN (0x1u << 8) |
| | (UART_PTSR) Transmitter Transfer Enable
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1.8.11 
