component_can.h

/* ----------------------------------------------------------------------------
 *         SAM Software Package License
 * ----------------------------------------------------------------------------
 * Copyright (c) 2012, Atmel Corporation
 *
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following condition is met:
 *
 * - Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the disclaimer below.
 *
 * Atmel's name may not be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
 * DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
 * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
 * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 * ----------------------------------------------------------------------------
 */

#ifndef _SAM3XA_CAN_COMPONENT_
#define _SAM3XA_CAN_COMPONENT_

/* ============================================================================= */
/* ============================================================================= */

#if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__))

typedef struct {
  RwReg  CAN_MMR;       
  RwReg  CAN_MAM;       
  RwReg  CAN_MID;       
  RwReg  CAN_MFID;      
  RwReg  CAN_MSR;       
  RwReg  CAN_MDL;       
  RwReg  CAN_MDH;       
  RwReg  CAN_MCR;       
} CanMb;
#define CANMB_NUMBER 8
typedef struct {
  RwReg  CAN_MR;        
  WoReg  CAN_IER;       
  WoReg  CAN_IDR;       
  RoReg  CAN_IMR;       
  RoReg  CAN_SR;        
  RwReg  CAN_BR;        
  RoReg  CAN_TIM;       
  RoReg  CAN_TIMESTP;   
  RoReg  CAN_ECR;       
  WoReg  CAN_TCR;       
  WoReg  CAN_ACR;       
  RoReg  Reserved1[46];
  RwReg  CAN_WPMR;      
  RoReg  CAN_WPSR;      
  RoReg  Reserved2[69];
  CanMb  CAN_MB[CANMB_NUMBER]; 
} Can;
#endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */
/* -------- CAN_MR : (CAN Offset: 0x0000) Mode Register -------- */
#define CAN_MR_CANEN (0x1u << 0) 
#define CAN_MR_LPM (0x1u << 1) 
#define CAN_MR_ABM (0x1u << 2) 
#define CAN_MR_OVL (0x1u << 3) 
#define CAN_MR_TEOF (0x1u << 4) 
#define CAN_MR_TTM (0x1u << 5) 
#define CAN_MR_TIMFRZ (0x1u << 6) 
#define CAN_MR_DRPT (0x1u << 7) 
#define CAN_MR_RXSYNC_Pos 24
#define CAN_MR_RXSYNC_Msk (0x7u << CAN_MR_RXSYNC_Pos) 
#define   CAN_MR_RXSYNC_DOUBLE_PP (0x0u << 24) 
#define   CAN_MR_RXSYNC_DOUBLE_PN (0x1u << 24) 
#define   CAN_MR_RXSYNC_SINGLE_P (0x2u << 24) 
#define   CAN_MR_RXSYNC_NONE (0x3u << 24) 
/* -------- CAN_IER : (CAN Offset: 0x0004) Interrupt Enable Register -------- */
#define CAN_IER_MB0 (0x1u << 0) 
#define CAN_IER_MB1 (0x1u << 1) 
#define CAN_IER_MB2 (0x1u << 2) 
#define CAN_IER_MB3 (0x1u << 3) 
#define CAN_IER_MB4 (0x1u << 4) 
#define CAN_IER_MB5 (0x1u << 5) 
#define CAN_IER_MB6 (0x1u << 6) 
#define CAN_IER_MB7 (0x1u << 7) 
#define CAN_IER_ERRA (0x1u << 16) 
#define CAN_IER_WARN (0x1u << 17) 
#define CAN_IER_ERRP (0x1u << 18) 
#define CAN_IER_BOFF (0x1u << 19) 
#define CAN_IER_SLEEP (0x1u << 20) 
#define CAN_IER_WAKEUP (0x1u << 21) 
#define CAN_IER_TOVF (0x1u << 22) 
#define CAN_IER_TSTP (0x1u << 23) 
#define CAN_IER_CERR (0x1u << 24) 
#define CAN_IER_SERR (0x1u << 25) 
#define CAN_IER_AERR (0x1u << 26) 
#define CAN_IER_FERR (0x1u << 27) 
#define CAN_IER_BERR (0x1u << 28) 
/* -------- CAN_IDR : (CAN Offset: 0x0008) Interrupt Disable Register -------- */
#define CAN_IDR_MB0 (0x1u << 0) 
#define CAN_IDR_MB1 (0x1u << 1) 
#define CAN_IDR_MB2 (0x1u << 2) 
#define CAN_IDR_MB3 (0x1u << 3) 
#define CAN_IDR_MB4 (0x1u << 4) 
#define CAN_IDR_MB5 (0x1u << 5) 
#define CAN_IDR_MB6 (0x1u << 6) 
#define CAN_IDR_MB7 (0x1u << 7) 
#define CAN_IDR_ERRA (0x1u << 16) 
#define CAN_IDR_WARN (0x1u << 17) 
#define CAN_IDR_ERRP (0x1u << 18) 
#define CAN_IDR_BOFF (0x1u << 19) 
#define CAN_IDR_SLEEP (0x1u << 20) 
#define CAN_IDR_WAKEUP (0x1u << 21) 
#define CAN_IDR_TOVF (0x1u << 22) 
#define CAN_IDR_TSTP (0x1u << 23) 
#define CAN_IDR_CERR (0x1u << 24) 
#define CAN_IDR_SERR (0x1u << 25) 
#define CAN_IDR_AERR (0x1u << 26) 
#define CAN_IDR_FERR (0x1u << 27) 
#define CAN_IDR_BERR (0x1u << 28) 
/* -------- CAN_IMR : (CAN Offset: 0x000C) Interrupt Mask Register -------- */
#define CAN_IMR_MB0 (0x1u << 0) 
#define CAN_IMR_MB1 (0x1u << 1) 
#define CAN_IMR_MB2 (0x1u << 2) 
#define CAN_IMR_MB3 (0x1u << 3) 
#define CAN_IMR_MB4 (0x1u << 4) 
#define CAN_IMR_MB5 (0x1u << 5) 
#define CAN_IMR_MB6 (0x1u << 6) 
#define CAN_IMR_MB7 (0x1u << 7) 
#define CAN_IMR_ERRA (0x1u << 16) 
#define CAN_IMR_WARN (0x1u << 17) 
#define CAN_IMR_ERRP (0x1u << 18) 
#define CAN_IMR_BOFF (0x1u << 19) 
#define CAN_IMR_SLEEP (0x1u << 20) 
#define CAN_IMR_WAKEUP (0x1u << 21) 
#define CAN_IMR_TOVF (0x1u << 22) 
#define CAN_IMR_TSTP (0x1u << 23) 
#define CAN_IMR_CERR (0x1u << 24) 
#define CAN_IMR_SERR (0x1u << 25) 
#define CAN_IMR_AERR (0x1u << 26) 
#define CAN_IMR_FERR (0x1u << 27) 
#define CAN_IMR_BERR (0x1u << 28) 
/* -------- CAN_SR : (CAN Offset: 0x0010) Status Register -------- */
#define CAN_SR_MB0 (0x1u << 0) 
#define CAN_SR_MB1 (0x1u << 1) 
#define CAN_SR_MB2 (0x1u << 2) 
#define CAN_SR_MB3 (0x1u << 3) 
#define CAN_SR_MB4 (0x1u << 4) 
#define CAN_SR_MB5 (0x1u << 5) 
#define CAN_SR_MB6 (0x1u << 6) 
#define CAN_SR_MB7 (0x1u << 7) 
#define CAN_SR_ERRA (0x1u << 16) 
#define CAN_SR_WARN (0x1u << 17) 
#define CAN_SR_ERRP (0x1u << 18) 
#define CAN_SR_BOFF (0x1u << 19) 
#define CAN_SR_SLEEP (0x1u << 20) 
#define CAN_SR_WAKEUP (0x1u << 21) 
#define CAN_SR_TOVF (0x1u << 22) 
#define CAN_SR_TSTP (0x1u << 23) 
#define CAN_SR_CERR (0x1u << 24) 
#define CAN_SR_SERR (0x1u << 25) 
#define CAN_SR_AERR (0x1u << 26) 
#define CAN_SR_FERR (0x1u << 27) 
#define CAN_SR_BERR (0x1u << 28) 
#define CAN_SR_RBSY (0x1u << 29) 
#define CAN_SR_TBSY (0x1u << 30) 
#define CAN_SR_OVLSY (0x1u << 31) 
/* -------- CAN_BR : (CAN Offset: 0x0014) Baudrate Register -------- */
#define CAN_BR_PHASE2_Pos 0
#define CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) 
#define CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos)))
#define CAN_BR_PHASE1_Pos 4
#define CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) 
#define CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos)))
#define CAN_BR_PROPAG_Pos 8
#define CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) 
#define CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos)))
#define CAN_BR_SJW_Pos 12
#define CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) 
#define CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos)))
#define CAN_BR_BRP_Pos 16
#define CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) 
#define CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos)))
#define CAN_BR_SMP (0x1u << 24) 
#define   CAN_BR_SMP_ONCE (0x0u << 24) 
#define   CAN_BR_SMP_THREE (0x1u << 24) 
/* -------- CAN_TIM : (CAN Offset: 0x0018) Timer Register -------- */
#define CAN_TIM_TIMER_Pos 0
#define CAN_TIM_TIMER_Msk (0xffffu << CAN_TIM_TIMER_Pos) 
/* -------- CAN_TIMESTP : (CAN Offset: 0x001C) Timestamp Register -------- */
#define CAN_TIMESTP_MTIMESTAMP_Pos 0
#define CAN_TIMESTP_MTIMESTAMP_Msk (0xffffu << CAN_TIMESTP_MTIMESTAMP_Pos) 
/* -------- CAN_ECR : (CAN Offset: 0x0020) Error Counter Register -------- */
#define CAN_ECR_REC_Pos 0
#define CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) 
#define CAN_ECR_TEC_Pos 16
#define CAN_ECR_TEC_Msk (0xffu << CAN_ECR_TEC_Pos) 
/* -------- CAN_TCR : (CAN Offset: 0x0024) Transfer Command Register -------- */
#define CAN_TCR_MB0 (0x1u << 0) 
#define CAN_TCR_MB1 (0x1u << 1) 
#define CAN_TCR_MB2 (0x1u << 2) 
#define CAN_TCR_MB3 (0x1u << 3) 
#define CAN_TCR_MB4 (0x1u << 4) 
#define CAN_TCR_MB5 (0x1u << 5) 
#define CAN_TCR_MB6 (0x1u << 6) 
#define CAN_TCR_MB7 (0x1u << 7) 
#define CAN_TCR_TIMRST (0x1u << 31) 
/* -------- CAN_ACR : (CAN Offset: 0x0028) Abort Command Register -------- */
#define CAN_ACR_MB0 (0x1u << 0) 
#define CAN_ACR_MB1 (0x1u << 1) 
#define CAN_ACR_MB2 (0x1u << 2) 
#define CAN_ACR_MB3 (0x1u << 3) 
#define CAN_ACR_MB4 (0x1u << 4) 
#define CAN_ACR_MB5 (0x1u << 5) 
#define CAN_ACR_MB6 (0x1u << 6) 
#define CAN_ACR_MB7 (0x1u << 7) 
/* -------- CAN_WPMR : (CAN Offset: 0x00E4) Write Protect Mode Register -------- */
#define CAN_WPMR_WPEN (0x1u << 0) 
#define CAN_WPMR_WPKEY_Pos 8
#define CAN_WPMR_WPKEY_Msk (0xffffffu << CAN_WPMR_WPKEY_Pos) 
#define CAN_WPMR_WPKEY(value) ((CAN_WPMR_WPKEY_Msk & ((value) << CAN_WPMR_WPKEY_Pos)))
/* -------- CAN_WPSR : (CAN Offset: 0x00E8) Write Protect Status Register -------- */
#define CAN_WPSR_WPVS (0x1u << 0) 
#define CAN_WPSR_WPVSRC_Pos 8
#define CAN_WPSR_WPVSRC_Msk (0xffu << CAN_WPSR_WPVSRC_Pos) 
/* -------- CAN_MMR : (CAN Offset: N/A) Mailbox Mode Register -------- */
#define CAN_MMR_MTIMEMARK_Pos 0
#define CAN_MMR_MTIMEMARK_Msk (0xffffu << CAN_MMR_MTIMEMARK_Pos) 
#define CAN_MMR_MTIMEMARK(value) ((CAN_MMR_MTIMEMARK_Msk & ((value) << CAN_MMR_MTIMEMARK_Pos)))
#define CAN_MMR_PRIOR_Pos 16
#define CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) 
#define CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos)))
#define CAN_MMR_MOT_Pos 24
#define CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) 
#define   CAN_MMR_MOT_MB_DISABLED (0x0u << 24) 
#define   CAN_MMR_MOT_MB_RX (0x1u << 24) 
#define   CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) 
#define   CAN_MMR_MOT_MB_TX (0x3u << 24) 
#define   CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) 
#define   CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) 
/* -------- CAN_MAM : (CAN Offset: N/A) Mailbox Acceptance Mask Register -------- */
#define CAN_MAM_MIDvB_Pos 0
#define CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) 
#define CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos)))
#define CAN_MAM_MIDvA_Pos 18
#define CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) 
#define CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos)))
#define CAN_MAM_MIDE (0x1u << 29) 
/* -------- CAN_MID : (CAN Offset: N/A) Mailbox ID Register -------- */
#define CAN_MID_MIDvB_Pos 0
#define CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) 
#define CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos)))
#define CAN_MID_MIDvA_Pos 18
#define CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) 
#define CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos)))
#define CAN_MID_MIDE (0x1u << 29) 
/* -------- CAN_MFID : (CAN Offset: N/A) Mailbox Family ID Register -------- */
#define CAN_MFID_MFID_Pos 0
#define CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) 
/* -------- CAN_MSR : (CAN Offset: N/A) Mailbox Status Register -------- */
#define CAN_MSR_MTIMESTAMP_Pos 0
#define CAN_MSR_MTIMESTAMP_Msk (0xffffu << CAN_MSR_MTIMESTAMP_Pos) 
#define CAN_MSR_MDLC_Pos 16
#define CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) 
#define CAN_MSR_MRTR (0x1u << 20) 
#define CAN_MSR_MABT (0x1u << 22) 
#define CAN_MSR_MRDY (0x1u << 23) 
#define CAN_MSR_MMI (0x1u << 24) 
/* -------- CAN_MDL : (CAN Offset: N/A) Mailbox Data Low Register -------- */
#define CAN_MDL_MDL_Pos 0
#define CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) 
#define CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos)))
/* -------- CAN_MDH : (CAN Offset: N/A) Mailbox Data High Register -------- */
#define CAN_MDH_MDH_Pos 0
#define CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) 
#define CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos)))
/* -------- CAN_MCR : (CAN Offset: N/A) Mailbox Control Register -------- */
#define CAN_MCR_MDLC_Pos 16
#define CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) 
#define CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos)))
#define CAN_MCR_MRTR (0x1u << 20) 
#define CAN_MCR_MACR (0x1u << 22) 
#define CAN_MCR_MTCR (0x1u << 23) 


#endif /* _SAM3XA_CAN_COMPONENT_ */