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#define | CANMB_NUMBER 8 |
| | Can hardware registers.
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#define | CAN_MR_CANEN (0x1u << 0) |
| | (CAN_MR) CAN Controller Enable
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#define | CAN_MR_LPM (0x1u << 1) |
| | (CAN_MR) Disable/Enable Low Power Mode
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#define | CAN_MR_ABM (0x1u << 2) |
| | (CAN_MR) Disable/Enable Autobaud/Listen mode
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#define | CAN_MR_OVL (0x1u << 3) |
| | (CAN_MR) Disable/Enable Overload Frame
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#define | CAN_MR_TEOF (0x1u << 4) |
| | (CAN_MR) Timestamp messages at each end of Frame
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#define | CAN_MR_TTM (0x1u << 5) |
| | (CAN_MR) Disable/Enable Time Triggered Mode
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#define | CAN_MR_TIMFRZ (0x1u << 6) |
| | (CAN_MR) Enable Timer Freeze
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#define | CAN_MR_DRPT (0x1u << 7) |
| | (CAN_MR) Disable Repeat
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#define | CAN_MR_RXSYNC_Pos 24 |
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#define | CAN_MR_RXSYNC_Msk (0x7u << CAN_MR_RXSYNC_Pos) |
| | (CAN_MR) Reception Synchronization Stage (not readable)
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#define | CAN_MR_RXSYNC_DOUBLE_PP (0x0u << 24) |
| | (CAN_MR) Rx Signal with Double Synchro Stages (2 Positive Edges)
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#define | CAN_MR_RXSYNC_DOUBLE_PN (0x1u << 24) |
| | (CAN_MR) Rx Signal with Double Synchro Stages (One Positive Edge and One Negative Edge)
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#define | CAN_MR_RXSYNC_SINGLE_P (0x2u << 24) |
| | (CAN_MR) Rx Signal with Single Synchro Stage (Positive Edge)
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#define | CAN_MR_RXSYNC_NONE (0x3u << 24) |
| | (CAN_MR) Rx Signal with No Synchro Stage
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#define | CAN_IER_MB0 (0x1u << 0) |
| | (CAN_IER) Mailbox 0 Interrupt Enable
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#define | CAN_IER_MB1 (0x1u << 1) |
| | (CAN_IER) Mailbox 1 Interrupt Enable
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#define | CAN_IER_MB2 (0x1u << 2) |
| | (CAN_IER) Mailbox 2 Interrupt Enable
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#define | CAN_IER_MB3 (0x1u << 3) |
| | (CAN_IER) Mailbox 3 Interrupt Enable
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#define | CAN_IER_MB4 (0x1u << 4) |
| | (CAN_IER) Mailbox 4 Interrupt Enable
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#define | CAN_IER_MB5 (0x1u << 5) |
| | (CAN_IER) Mailbox 5 Interrupt Enable
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#define | CAN_IER_MB6 (0x1u << 6) |
| | (CAN_IER) Mailbox 6 Interrupt Enable
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#define | CAN_IER_MB7 (0x1u << 7) |
| | (CAN_IER) Mailbox 7 Interrupt Enable
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#define | CAN_IER_ERRA (0x1u << 16) |
| | (CAN_IER) Error Active Mode Interrupt Enable
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#define | CAN_IER_WARN (0x1u << 17) |
| | (CAN_IER) Warning Limit Interrupt Enable
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#define | CAN_IER_ERRP (0x1u << 18) |
| | (CAN_IER) Error Passive Mode Interrupt Enable
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#define | CAN_IER_BOFF (0x1u << 19) |
| | (CAN_IER) Bus Off Mode Interrupt Enable
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#define | CAN_IER_SLEEP (0x1u << 20) |
| | (CAN_IER) Sleep Interrupt Enable
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#define | CAN_IER_WAKEUP (0x1u << 21) |
| | (CAN_IER) Wakeup Interrupt Enable
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#define | CAN_IER_TOVF (0x1u << 22) |
| | (CAN_IER) Timer Overflow Interrupt Enable
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#define | CAN_IER_TSTP (0x1u << 23) |
| | (CAN_IER) TimeStamp Interrupt Enable
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#define | CAN_IER_CERR (0x1u << 24) |
| | (CAN_IER) CRC Error Interrupt Enable
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#define | CAN_IER_SERR (0x1u << 25) |
| | (CAN_IER) Stuffing Error Interrupt Enable
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#define | CAN_IER_AERR (0x1u << 26) |
| | (CAN_IER) Acknowledgment Error Interrupt Enable
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#define | CAN_IER_FERR (0x1u << 27) |
| | (CAN_IER) Form Error Interrupt Enable
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#define | CAN_IER_BERR (0x1u << 28) |
| | (CAN_IER) Bit Error Interrupt Enable
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#define | CAN_IDR_MB0 (0x1u << 0) |
| | (CAN_IDR) Mailbox 0 Interrupt Disable
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#define | CAN_IDR_MB1 (0x1u << 1) |
| | (CAN_IDR) Mailbox 1 Interrupt Disable
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#define | CAN_IDR_MB2 (0x1u << 2) |
| | (CAN_IDR) Mailbox 2 Interrupt Disable
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#define | CAN_IDR_MB3 (0x1u << 3) |
| | (CAN_IDR) Mailbox 3 Interrupt Disable
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#define | CAN_IDR_MB4 (0x1u << 4) |
| | (CAN_IDR) Mailbox 4 Interrupt Disable
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#define | CAN_IDR_MB5 (0x1u << 5) |
| | (CAN_IDR) Mailbox 5 Interrupt Disable
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#define | CAN_IDR_MB6 (0x1u << 6) |
| | (CAN_IDR) Mailbox 6 Interrupt Disable
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#define | CAN_IDR_MB7 (0x1u << 7) |
| | (CAN_IDR) Mailbox 7 Interrupt Disable
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#define | CAN_IDR_ERRA (0x1u << 16) |
| | (CAN_IDR) Error Active Mode Interrupt Disable
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#define | CAN_IDR_WARN (0x1u << 17) |
| | (CAN_IDR) Warning Limit Interrupt Disable
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#define | CAN_IDR_ERRP (0x1u << 18) |
| | (CAN_IDR) Error Passive Mode Interrupt Disable
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#define | CAN_IDR_BOFF (0x1u << 19) |
| | (CAN_IDR) Bus Off Mode Interrupt Disable
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#define | CAN_IDR_SLEEP (0x1u << 20) |
| | (CAN_IDR) Sleep Interrupt Disable
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#define | CAN_IDR_WAKEUP (0x1u << 21) |
| | (CAN_IDR) Wakeup Interrupt Disable
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#define | CAN_IDR_TOVF (0x1u << 22) |
| | (CAN_IDR) Timer Overflow Interrupt
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#define | CAN_IDR_TSTP (0x1u << 23) |
| | (CAN_IDR) TimeStamp Interrupt Disable
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#define | CAN_IDR_CERR (0x1u << 24) |
| | (CAN_IDR) CRC Error Interrupt Disable
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#define | CAN_IDR_SERR (0x1u << 25) |
| | (CAN_IDR) Stuffing Error Interrupt Disable
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#define | CAN_IDR_AERR (0x1u << 26) |
| | (CAN_IDR) Acknowledgment Error Interrupt Disable
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#define | CAN_IDR_FERR (0x1u << 27) |
| | (CAN_IDR) Form Error Interrupt Disable
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#define | CAN_IDR_BERR (0x1u << 28) |
| | (CAN_IDR) Bit Error Interrupt Disable
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#define | CAN_IMR_MB0 (0x1u << 0) |
| | (CAN_IMR) Mailbox 0 Interrupt Mask
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#define | CAN_IMR_MB1 (0x1u << 1) |
| | (CAN_IMR) Mailbox 1 Interrupt Mask
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#define | CAN_IMR_MB2 (0x1u << 2) |
| | (CAN_IMR) Mailbox 2 Interrupt Mask
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#define | CAN_IMR_MB3 (0x1u << 3) |
| | (CAN_IMR) Mailbox 3 Interrupt Mask
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#define | CAN_IMR_MB4 (0x1u << 4) |
| | (CAN_IMR) Mailbox 4 Interrupt Mask
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#define | CAN_IMR_MB5 (0x1u << 5) |
| | (CAN_IMR) Mailbox 5 Interrupt Mask
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#define | CAN_IMR_MB6 (0x1u << 6) |
| | (CAN_IMR) Mailbox 6 Interrupt Mask
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#define | CAN_IMR_MB7 (0x1u << 7) |
| | (CAN_IMR) Mailbox 7 Interrupt Mask
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#define | CAN_IMR_ERRA (0x1u << 16) |
| | (CAN_IMR) Error Active Mode Interrupt Mask
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#define | CAN_IMR_WARN (0x1u << 17) |
| | (CAN_IMR) Warning Limit Interrupt Mask
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#define | CAN_IMR_ERRP (0x1u << 18) |
| | (CAN_IMR) Error Passive Mode Interrupt Mask
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#define | CAN_IMR_BOFF (0x1u << 19) |
| | (CAN_IMR) Bus Off Mode Interrupt Mask
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#define | CAN_IMR_SLEEP (0x1u << 20) |
| | (CAN_IMR) Sleep Interrupt Mask
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#define | CAN_IMR_WAKEUP (0x1u << 21) |
| | (CAN_IMR) Wakeup Interrupt Mask
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#define | CAN_IMR_TOVF (0x1u << 22) |
| | (CAN_IMR) Timer Overflow Interrupt Mask
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#define | CAN_IMR_TSTP (0x1u << 23) |
| | (CAN_IMR) Timestamp Interrupt Mask
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#define | CAN_IMR_CERR (0x1u << 24) |
| | (CAN_IMR) CRC Error Interrupt Mask
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#define | CAN_IMR_SERR (0x1u << 25) |
| | (CAN_IMR) Stuffing Error Interrupt Mask
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#define | CAN_IMR_AERR (0x1u << 26) |
| | (CAN_IMR) Acknowledgment Error Interrupt Mask
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#define | CAN_IMR_FERR (0x1u << 27) |
| | (CAN_IMR) Form Error Interrupt Mask
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#define | CAN_IMR_BERR (0x1u << 28) |
| | (CAN_IMR) Bit Error Interrupt Mask
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#define | CAN_SR_MB0 (0x1u << 0) |
| | (CAN_SR) Mailbox 0 Event
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#define | CAN_SR_MB1 (0x1u << 1) |
| | (CAN_SR) Mailbox 1 Event
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#define | CAN_SR_MB2 (0x1u << 2) |
| | (CAN_SR) Mailbox 2 Event
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#define | CAN_SR_MB3 (0x1u << 3) |
| | (CAN_SR) Mailbox 3 Event
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#define | CAN_SR_MB4 (0x1u << 4) |
| | (CAN_SR) Mailbox 4 Event
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#define | CAN_SR_MB5 (0x1u << 5) |
| | (CAN_SR) Mailbox 5 Event
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#define | CAN_SR_MB6 (0x1u << 6) |
| | (CAN_SR) Mailbox 6 Event
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#define | CAN_SR_MB7 (0x1u << 7) |
| | (CAN_SR) Mailbox 7 Event
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#define | CAN_SR_ERRA (0x1u << 16) |
| | (CAN_SR) Error Active Mode
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#define | CAN_SR_WARN (0x1u << 17) |
| | (CAN_SR) Warning Limit
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#define | CAN_SR_ERRP (0x1u << 18) |
| | (CAN_SR) Error Passive Mode
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#define | CAN_SR_BOFF (0x1u << 19) |
| | (CAN_SR) Bus Off Mode
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#define | CAN_SR_SLEEP (0x1u << 20) |
| | (CAN_SR) CAN controller in Low power Mode
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#define | CAN_SR_WAKEUP (0x1u << 21) |
| | (CAN_SR) CAN controller is not in Low power Mode
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#define | CAN_SR_TOVF (0x1u << 22) |
| | (CAN_SR) Timer Overflow
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#define | CAN_SR_TSTP (0x1u << 23) |
| | (CAN_SR)
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#define | CAN_SR_CERR (0x1u << 24) |
| | (CAN_SR) Mailbox CRC Error
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#define | CAN_SR_SERR (0x1u << 25) |
| | (CAN_SR) Mailbox Stuffing Error
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#define | CAN_SR_AERR (0x1u << 26) |
| | (CAN_SR) Acknowledgment Error
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#define | CAN_SR_FERR (0x1u << 27) |
| | (CAN_SR) Form Error
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#define | CAN_SR_BERR (0x1u << 28) |
| | (CAN_SR) Bit Error
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#define | CAN_SR_RBSY (0x1u << 29) |
| | (CAN_SR) Receiver busy
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#define | CAN_SR_TBSY (0x1u << 30) |
| | (CAN_SR) Transmitter busy
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#define | CAN_SR_OVLSY (0x1u << 31) |
| | (CAN_SR) Overload busy
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#define | CAN_BR_PHASE2_Pos 0 |
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#define | CAN_BR_PHASE2_Msk (0x7u << CAN_BR_PHASE2_Pos) |
| | (CAN_BR) Phase 2 segment
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#define | CAN_BR_PHASE2(value) ((CAN_BR_PHASE2_Msk & ((value) << CAN_BR_PHASE2_Pos))) |
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#define | CAN_BR_PHASE1_Pos 4 |
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#define | CAN_BR_PHASE1_Msk (0x7u << CAN_BR_PHASE1_Pos) |
| | (CAN_BR) Phase 1 segment
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#define | CAN_BR_PHASE1(value) ((CAN_BR_PHASE1_Msk & ((value) << CAN_BR_PHASE1_Pos))) |
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#define | CAN_BR_PROPAG_Pos 8 |
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#define | CAN_BR_PROPAG_Msk (0x7u << CAN_BR_PROPAG_Pos) |
| | (CAN_BR) Programming time segment
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#define | CAN_BR_PROPAG(value) ((CAN_BR_PROPAG_Msk & ((value) << CAN_BR_PROPAG_Pos))) |
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#define | CAN_BR_SJW_Pos 12 |
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#define | CAN_BR_SJW_Msk (0x3u << CAN_BR_SJW_Pos) |
| | (CAN_BR) Re-synchronization jump width
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#define | CAN_BR_SJW(value) ((CAN_BR_SJW_Msk & ((value) << CAN_BR_SJW_Pos))) |
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#define | CAN_BR_BRP_Pos 16 |
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#define | CAN_BR_BRP_Msk (0x7fu << CAN_BR_BRP_Pos) |
| | (CAN_BR) Baudrate Prescaler.
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#define | CAN_BR_BRP(value) ((CAN_BR_BRP_Msk & ((value) << CAN_BR_BRP_Pos))) |
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#define | CAN_BR_SMP (0x1u << 24) |
| | (CAN_BR) Sampling Mode
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#define | CAN_BR_SMP_ONCE (0x0u << 24) |
| | (CAN_BR) The incoming bit stream is sampled once at sample point.
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#define | CAN_BR_SMP_THREE (0x1u << 24) |
| | (CAN_BR) The incoming bit stream is sampled three times with a period of a MCK clock period, centered on sample point.
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#define | CAN_TIM_TIMER_Pos 0 |
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#define | CAN_TIM_TIMER_Msk (0xffffu << CAN_TIM_TIMER_Pos) |
| | (CAN_TIM) Timer
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#define | CAN_TIMESTP_MTIMESTAMP_Pos 0 |
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#define | CAN_TIMESTP_MTIMESTAMP_Msk (0xffffu << CAN_TIMESTP_MTIMESTAMP_Pos) |
| | (CAN_TIMESTP) Timestamp
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#define | CAN_ECR_REC_Pos 0 |
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#define | CAN_ECR_REC_Msk (0xffu << CAN_ECR_REC_Pos) |
| | (CAN_ECR) Receive Error Counter
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#define | CAN_ECR_TEC_Pos 16 |
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#define | CAN_ECR_TEC_Msk (0xffu << CAN_ECR_TEC_Pos) |
| | (CAN_ECR) Transmit Error Counter
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#define | CAN_TCR_MB0 (0x1u << 0) |
| | (CAN_TCR) Transfer Request for Mailbox 0
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#define | CAN_TCR_MB1 (0x1u << 1) |
| | (CAN_TCR) Transfer Request for Mailbox 1
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#define | CAN_TCR_MB2 (0x1u << 2) |
| | (CAN_TCR) Transfer Request for Mailbox 2
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#define | CAN_TCR_MB3 (0x1u << 3) |
| | (CAN_TCR) Transfer Request for Mailbox 3
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#define | CAN_TCR_MB4 (0x1u << 4) |
| | (CAN_TCR) Transfer Request for Mailbox 4
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#define | CAN_TCR_MB5 (0x1u << 5) |
| | (CAN_TCR) Transfer Request for Mailbox 5
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#define | CAN_TCR_MB6 (0x1u << 6) |
| | (CAN_TCR) Transfer Request for Mailbox 6
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#define | CAN_TCR_MB7 (0x1u << 7) |
| | (CAN_TCR) Transfer Request for Mailbox 7
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#define | CAN_TCR_TIMRST (0x1u << 31) |
| | (CAN_TCR) Timer Reset
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#define | CAN_ACR_MB0 (0x1u << 0) |
| | (CAN_ACR) Abort Request for Mailbox 0
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#define | CAN_ACR_MB1 (0x1u << 1) |
| | (CAN_ACR) Abort Request for Mailbox 1
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#define | CAN_ACR_MB2 (0x1u << 2) |
| | (CAN_ACR) Abort Request for Mailbox 2
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#define | CAN_ACR_MB3 (0x1u << 3) |
| | (CAN_ACR) Abort Request for Mailbox 3
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#define | CAN_ACR_MB4 (0x1u << 4) |
| | (CAN_ACR) Abort Request for Mailbox 4
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#define | CAN_ACR_MB5 (0x1u << 5) |
| | (CAN_ACR) Abort Request for Mailbox 5
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#define | CAN_ACR_MB6 (0x1u << 6) |
| | (CAN_ACR) Abort Request for Mailbox 6
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#define | CAN_ACR_MB7 (0x1u << 7) |
| | (CAN_ACR) Abort Request for Mailbox 7
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#define | CAN_WPMR_WPEN (0x1u << 0) |
| | (CAN_WPMR) Write Protection Enable
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#define | CAN_WPMR_WPKEY_Pos 8 |
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#define | CAN_WPMR_WPKEY_Msk (0xffffffu << CAN_WPMR_WPKEY_Pos) |
| | (CAN_WPMR) SPI Write Protection Key Password
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#define | CAN_WPMR_WPKEY(value) ((CAN_WPMR_WPKEY_Msk & ((value) << CAN_WPMR_WPKEY_Pos))) |
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#define | CAN_WPSR_WPVS (0x1u << 0) |
| | (CAN_WPSR) Write Protection Violation Status
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#define | CAN_WPSR_WPVSRC_Pos 8 |
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#define | CAN_WPSR_WPVSRC_Msk (0xffu << CAN_WPSR_WPVSRC_Pos) |
| | (CAN_WPSR) Write Protection Violation Source
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#define | CAN_MMR_MTIMEMARK_Pos 0 |
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#define | CAN_MMR_MTIMEMARK_Msk (0xffffu << CAN_MMR_MTIMEMARK_Pos) |
| | (CAN_MMR) Mailbox Timemark
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#define | CAN_MMR_MTIMEMARK(value) ((CAN_MMR_MTIMEMARK_Msk & ((value) << CAN_MMR_MTIMEMARK_Pos))) |
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#define | CAN_MMR_PRIOR_Pos 16 |
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#define | CAN_MMR_PRIOR_Msk (0xfu << CAN_MMR_PRIOR_Pos) |
| | (CAN_MMR) Mailbox Priority
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#define | CAN_MMR_PRIOR(value) ((CAN_MMR_PRIOR_Msk & ((value) << CAN_MMR_PRIOR_Pos))) |
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#define | CAN_MMR_MOT_Pos 24 |
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#define | CAN_MMR_MOT_Msk (0x7u << CAN_MMR_MOT_Pos) |
| | (CAN_MMR) Mailbox Object Type
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#define | CAN_MMR_MOT_MB_DISABLED (0x0u << 24) |
| | (CAN_MMR) Mailbox is disabled. This prevents receiving or transmitting any messages with this mailbox.
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#define | CAN_MMR_MOT_MB_RX (0x1u << 24) |
| | (CAN_MMR) Reception Mailbox. Mailbox is configured for reception. If a message is received while the mailbox data register is full, it is discarded.
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#define | CAN_MMR_MOT_MB_RX_OVERWRITE (0x2u << 24) |
| | (CAN_MMR) Reception mailbox with overwrite. Mailbox is configured for reception. If a message is received while the mailbox is full, it overwrites the previous message.
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#define | CAN_MMR_MOT_MB_TX (0x3u << 24) |
| | (CAN_MMR) Transmit mailbox. Mailbox is configured for transmission.
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#define | CAN_MMR_MOT_MB_CONSUMER (0x4u << 24) |
| | (CAN_MMR) Consumer Mailbox. Mailbox is configured in reception but behaves as a Transmit Mailbox, i.e., it sends a remote frame and waits for an answer.
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#define | CAN_MMR_MOT_MB_PRODUCER (0x5u << 24) |
| | (CAN_MMR) Producer Mailbox. Mailbox is configured in transmission but also behaves like a reception mailbox, i.e., it waits to receive a Remote Frame before sending its contents.
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#define | CAN_MAM_MIDvB_Pos 0 |
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#define | CAN_MAM_MIDvB_Msk (0x3ffffu << CAN_MAM_MIDvB_Pos) |
| | (CAN_MAM) Complementary bits for identifier in extended frame mode
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#define | CAN_MAM_MIDvB(value) ((CAN_MAM_MIDvB_Msk & ((value) << CAN_MAM_MIDvB_Pos))) |
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#define | CAN_MAM_MIDvA_Pos 18 |
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#define | CAN_MAM_MIDvA_Msk (0x7ffu << CAN_MAM_MIDvA_Pos) |
| | (CAN_MAM) Identifier for standard frame mode
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#define | CAN_MAM_MIDvA(value) ((CAN_MAM_MIDvA_Msk & ((value) << CAN_MAM_MIDvA_Pos))) |
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#define | CAN_MAM_MIDE (0x1u << 29) |
| | (CAN_MAM) Identifier Version
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#define | CAN_MID_MIDvB_Pos 0 |
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#define | CAN_MID_MIDvB_Msk (0x3ffffu << CAN_MID_MIDvB_Pos) |
| | (CAN_MID) Complementary bits for identifier in extended frame mode
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#define | CAN_MID_MIDvB(value) ((CAN_MID_MIDvB_Msk & ((value) << CAN_MID_MIDvB_Pos))) |
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#define | CAN_MID_MIDvA_Pos 18 |
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#define | CAN_MID_MIDvA_Msk (0x7ffu << CAN_MID_MIDvA_Pos) |
| | (CAN_MID) Identifier for standard frame mode
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#define | CAN_MID_MIDvA(value) ((CAN_MID_MIDvA_Msk & ((value) << CAN_MID_MIDvA_Pos))) |
| |
|
#define | CAN_MID_MIDE (0x1u << 29) |
| | (CAN_MID) Identifier Version
|
| |
|
#define | CAN_MFID_MFID_Pos 0 |
| |
|
#define | CAN_MFID_MFID_Msk (0x1fffffffu << CAN_MFID_MFID_Pos) |
| | (CAN_MFID) Family ID
|
| |
|
#define | CAN_MSR_MTIMESTAMP_Pos 0 |
| |
|
#define | CAN_MSR_MTIMESTAMP_Msk (0xffffu << CAN_MSR_MTIMESTAMP_Pos) |
| | (CAN_MSR) Timer value
|
| |
|
#define | CAN_MSR_MDLC_Pos 16 |
| |
|
#define | CAN_MSR_MDLC_Msk (0xfu << CAN_MSR_MDLC_Pos) |
| | (CAN_MSR) Mailbox Data Length Code
|
| |
|
#define | CAN_MSR_MRTR (0x1u << 20) |
| | (CAN_MSR) Mailbox Remote Transmission Request
|
| |
|
#define | CAN_MSR_MABT (0x1u << 22) |
| | (CAN_MSR) Mailbox Message Abort
|
| |
|
#define | CAN_MSR_MRDY (0x1u << 23) |
| | (CAN_MSR) Mailbox Ready
|
| |
|
#define | CAN_MSR_MMI (0x1u << 24) |
| | (CAN_MSR) Mailbox Message Ignored
|
| |
|
#define | CAN_MDL_MDL_Pos 0 |
| |
|
#define | CAN_MDL_MDL_Msk (0xffffffffu << CAN_MDL_MDL_Pos) |
| | (CAN_MDL) Message Data Low Value
|
| |
|
#define | CAN_MDL_MDL(value) ((CAN_MDL_MDL_Msk & ((value) << CAN_MDL_MDL_Pos))) |
| |
|
#define | CAN_MDH_MDH_Pos 0 |
| |
|
#define | CAN_MDH_MDH_Msk (0xffffffffu << CAN_MDH_MDH_Pos) |
| | (CAN_MDH) Message Data High Value
|
| |
|
#define | CAN_MDH_MDH(value) ((CAN_MDH_MDH_Msk & ((value) << CAN_MDH_MDH_Pos))) |
| |
|
#define | CAN_MCR_MDLC_Pos 16 |
| |
|
#define | CAN_MCR_MDLC_Msk (0xfu << CAN_MCR_MDLC_Pos) |
| | (CAN_MCR) Mailbox Data Length Code
|
| |
|
#define | CAN_MCR_MDLC(value) ((CAN_MCR_MDLC_Msk & ((value) << CAN_MCR_MDLC_Pos))) |
| |
|
#define | CAN_MCR_MRTR (0x1u << 20) |
| | (CAN_MCR) Mailbox Remote Transmission Request
|
| |
|
#define | CAN_MCR_MACR (0x1u << 22) |
| | (CAN_MCR) Abort Request for Mailbox x
|
| |
|
#define | CAN_MCR_MTCR (0x1u << 23) |
| | (CAN_MCR) Mailbox Transfer Command
|
| |
1.8.11 
