Classes
struct	Matrix
	Matrix hardware registers. More...

Macros
#define	MATRIX_MCFG_ULBT_Pos 0

#define	MATRIX_MCFG_ULBT_Msk (0x7u << MATRIX_MCFG_ULBT_Pos)
	(MATRIX_MCFG[3]) Undefined Length Burst Type

#define	MATRIX_MCFG_ULBT(value) ((MATRIX_MCFG_ULBT_Msk & ((value) << MATRIX_MCFG_ULBT_Pos)))

#define	MATRIX_SCFG_SLOT_CYCLE_Pos 0

#define	MATRIX_SCFG_SLOT_CYCLE_Msk (0xffu << MATRIX_SCFG_SLOT_CYCLE_Pos)
	(MATRIX_SCFG[4]) Maximum Number of Allowed Cycles for a Burst

#define	MATRIX_SCFG_SLOT_CYCLE(value) ((MATRIX_SCFG_SLOT_CYCLE_Msk & ((value) << MATRIX_SCFG_SLOT_CYCLE_Pos)))

#define	MATRIX_SCFG_DEFMSTR_TYPE_Pos 16

#define	MATRIX_SCFG_DEFMSTR_TYPE_Msk (0x3u << MATRIX_SCFG_DEFMSTR_TYPE_Pos)
	(MATRIX_SCFG[4]) Default Master Type

#define	MATRIX_SCFG_DEFMSTR_TYPE(value) ((MATRIX_SCFG_DEFMSTR_TYPE_Msk & ((value) << MATRIX_SCFG_DEFMSTR_TYPE_Pos)))

#define	MATRIX_SCFG_FIXED_DEFMSTR_Pos 18

#define	MATRIX_SCFG_FIXED_DEFMSTR_Msk (0x7u << MATRIX_SCFG_FIXED_DEFMSTR_Pos)
	(MATRIX_SCFG[4]) Fixed Default Master

#define	MATRIX_SCFG_FIXED_DEFMSTR(value) ((MATRIX_SCFG_FIXED_DEFMSTR_Msk & ((value) << MATRIX_SCFG_FIXED_DEFMSTR_Pos)))

#define	MATRIX_SCFG_ARBT_Pos 24

#define	MATRIX_SCFG_ARBT_Msk (0x3u << MATRIX_SCFG_ARBT_Pos)
	(MATRIX_SCFG[4]) Arbitration Type

#define	MATRIX_SCFG_ARBT(value) ((MATRIX_SCFG_ARBT_Msk & ((value) << MATRIX_SCFG_ARBT_Pos)))

#define	MATRIX_PRAS0_M0PR_Pos 0

#define	MATRIX_PRAS0_M0PR_Msk (0x3u << MATRIX_PRAS0_M0PR_Pos)
	(MATRIX_PRAS0) Master 0 Priority

#define	MATRIX_PRAS0_M0PR(value) ((MATRIX_PRAS0_M0PR_Msk & ((value) << MATRIX_PRAS0_M0PR_Pos)))

#define	MATRIX_PRAS0_M1PR_Pos 4

#define	MATRIX_PRAS0_M1PR_Msk (0x3u << MATRIX_PRAS0_M1PR_Pos)
	(MATRIX_PRAS0) Master 1 Priority

#define	MATRIX_PRAS0_M1PR(value) ((MATRIX_PRAS0_M1PR_Msk & ((value) << MATRIX_PRAS0_M1PR_Pos)))

#define	MATRIX_PRAS0_M2PR_Pos 8

#define	MATRIX_PRAS0_M2PR_Msk (0x3u << MATRIX_PRAS0_M2PR_Pos)
	(MATRIX_PRAS0) Master 2 Priority

#define	MATRIX_PRAS0_M2PR(value) ((MATRIX_PRAS0_M2PR_Msk & ((value) << MATRIX_PRAS0_M2PR_Pos)))

#define	MATRIX_PRAS0_M3PR_Pos 12

#define	MATRIX_PRAS0_M3PR_Msk (0x3u << MATRIX_PRAS0_M3PR_Pos)
	(MATRIX_PRAS0) Master 3 Priority

#define	MATRIX_PRAS0_M3PR(value) ((MATRIX_PRAS0_M3PR_Msk & ((value) << MATRIX_PRAS0_M3PR_Pos)))

#define	MATRIX_PRAS1_M0PR_Pos 0

#define	MATRIX_PRAS1_M0PR_Msk (0x3u << MATRIX_PRAS1_M0PR_Pos)
	(MATRIX_PRAS1) Master 0 Priority

#define	MATRIX_PRAS1_M0PR(value) ((MATRIX_PRAS1_M0PR_Msk & ((value) << MATRIX_PRAS1_M0PR_Pos)))

#define	MATRIX_PRAS1_M1PR_Pos 4

#define	MATRIX_PRAS1_M1PR_Msk (0x3u << MATRIX_PRAS1_M1PR_Pos)
	(MATRIX_PRAS1) Master 1 Priority

#define	MATRIX_PRAS1_M1PR(value) ((MATRIX_PRAS1_M1PR_Msk & ((value) << MATRIX_PRAS1_M1PR_Pos)))

#define	MATRIX_PRAS1_M2PR_Pos 8

#define	MATRIX_PRAS1_M2PR_Msk (0x3u << MATRIX_PRAS1_M2PR_Pos)
	(MATRIX_PRAS1) Master 2 Priority

#define	MATRIX_PRAS1_M2PR(value) ((MATRIX_PRAS1_M2PR_Msk & ((value) << MATRIX_PRAS1_M2PR_Pos)))

#define	MATRIX_PRAS1_M3PR_Pos 12

#define	MATRIX_PRAS1_M3PR_Msk (0x3u << MATRIX_PRAS1_M3PR_Pos)
	(MATRIX_PRAS1) Master 3 Priority

#define	MATRIX_PRAS1_M3PR(value) ((MATRIX_PRAS1_M3PR_Msk & ((value) << MATRIX_PRAS1_M3PR_Pos)))

#define	MATRIX_PRAS2_M0PR_Pos 0

#define	MATRIX_PRAS2_M0PR_Msk (0x3u << MATRIX_PRAS2_M0PR_Pos)
	(MATRIX_PRAS2) Master 0 Priority

#define	MATRIX_PRAS2_M0PR(value) ((MATRIX_PRAS2_M0PR_Msk & ((value) << MATRIX_PRAS2_M0PR_Pos)))

#define	MATRIX_PRAS2_M1PR_Pos 4

#define	MATRIX_PRAS2_M1PR_Msk (0x3u << MATRIX_PRAS2_M1PR_Pos)
	(MATRIX_PRAS2) Master 1 Priority

#define	MATRIX_PRAS2_M1PR(value) ((MATRIX_PRAS2_M1PR_Msk & ((value) << MATRIX_PRAS2_M1PR_Pos)))

#define	MATRIX_PRAS2_M2PR_Pos 8

#define	MATRIX_PRAS2_M2PR_Msk (0x3u << MATRIX_PRAS2_M2PR_Pos)
	(MATRIX_PRAS2) Master 2 Priority

#define	MATRIX_PRAS2_M2PR(value) ((MATRIX_PRAS2_M2PR_Msk & ((value) << MATRIX_PRAS2_M2PR_Pos)))

#define	MATRIX_PRAS2_M3PR_Pos 12

#define	MATRIX_PRAS2_M3PR_Msk (0x3u << MATRIX_PRAS2_M3PR_Pos)
	(MATRIX_PRAS2) Master 3 Priority

#define	MATRIX_PRAS2_M3PR(value) ((MATRIX_PRAS2_M3PR_Msk & ((value) << MATRIX_PRAS2_M3PR_Pos)))

#define	MATRIX_PRAS3_M0PR_Pos 0

#define	MATRIX_PRAS3_M0PR_Msk (0x3u << MATRIX_PRAS3_M0PR_Pos)
	(MATRIX_PRAS3) Master 0 Priority

#define	MATRIX_PRAS3_M0PR(value) ((MATRIX_PRAS3_M0PR_Msk & ((value) << MATRIX_PRAS3_M0PR_Pos)))

#define	MATRIX_PRAS3_M1PR_Pos 4

#define	MATRIX_PRAS3_M1PR_Msk (0x3u << MATRIX_PRAS3_M1PR_Pos)
	(MATRIX_PRAS3) Master 1 Priority

#define	MATRIX_PRAS3_M1PR(value) ((MATRIX_PRAS3_M1PR_Msk & ((value) << MATRIX_PRAS3_M1PR_Pos)))

#define	MATRIX_PRAS3_M2PR_Pos 8

#define	MATRIX_PRAS3_M2PR_Msk (0x3u << MATRIX_PRAS3_M2PR_Pos)
	(MATRIX_PRAS3) Master 2 Priority

#define	MATRIX_PRAS3_M2PR(value) ((MATRIX_PRAS3_M2PR_Msk & ((value) << MATRIX_PRAS3_M2PR_Pos)))

#define	MATRIX_PRAS3_M3PR_Pos 12

#define	MATRIX_PRAS3_M3PR_Msk (0x3u << MATRIX_PRAS3_M3PR_Pos)
	(MATRIX_PRAS3) Master 3 Priority

#define	MATRIX_PRAS3_M3PR(value) ((MATRIX_PRAS3_M3PR_Msk & ((value) << MATRIX_PRAS3_M3PR_Pos)))

#define	CCFG_SYSIO_SYSIO4 (0x1u << 4)
	(CCFG_SYSIO) PB4 or TDI Assignment

#define	CCFG_SYSIO_SYSIO5 (0x1u << 5)
	(CCFG_SYSIO) PB5 or TDO/TRACESWO Assignment

#define	CCFG_SYSIO_SYSIO6 (0x1u << 6)
	(CCFG_SYSIO) PB6 or TMS/SWDIO Assignment

#define	CCFG_SYSIO_SYSIO7 (0x1u << 7)
	(CCFG_SYSIO) PB7 or TCK/SWCLK Assignment

#define	CCFG_SYSIO_SYSIO12 (0x1u << 12)
	(CCFG_SYSIO) PB12 or ERASE Assignment

#define	MATRIX_WPMR_WPEN (0x1u << 0)
	(MATRIX_WPMR) Write Protect ENable

#define	MATRIX_WPMR_WPKEY_Pos 8

#define	MATRIX_WPMR_WPKEY_Msk (0xffffffu << MATRIX_WPMR_WPKEY_Pos)
	(MATRIX_WPMR) Write Protect KEY (Write-only)

#define	MATRIX_WPMR_WPKEY(value) ((MATRIX_WPMR_WPKEY_Msk & ((value) << MATRIX_WPMR_WPKEY_Pos)))

#define	MATRIX_WPSR_WPVS (0x1u << 0)
	(MATRIX_WPSR) Write Protect Violation Status

#define	MATRIX_WPSR_WPVSRC_Pos 8

#define	MATRIX_WPSR_WPVSRC_Msk (0xffffu << MATRIX_WPSR_WPVSRC_Pos)
	(MATRIX_WPSR) Write Protect Violation Source

Detailed Description

SOFTWARE API DEFINITION FOR AHB Bus Matrix

Classes

Macros

Detailed Description