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|
#define | ADC_CR_SWRST (0x1u << 0) |
| | (ADC_CR) Software Reset
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| |
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#define | ADC_CR_START (0x1u << 1) |
| | (ADC_CR) Start Conversion
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#define | ADC_MR_TRGEN (0x1u << 0) |
| | (ADC_MR) Trigger Enable
|
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#define | ADC_MR_TRGEN_DIS (0x0u << 0) |
| | (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.
|
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#define | ADC_MR_TRGEN_EN (0x1u << 0) |
| | (ADC_MR) Hardware trigger selected by TRGSEL field is enabled.
|
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#define | ADC_MR_TRGSEL_Pos 1 |
| |
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#define | ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) |
| | (ADC_MR) Trigger Selection
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#define | ADC_MR_TRGSEL_ADC_TRIG0 (0x0u << 1) |
| | (ADC_MR) External trigger
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#define | ADC_MR_TRGSEL_ADC_TRIG1 (0x1u << 1) |
| | (ADC_MR) TIO Output of the Timer Counter Channel 0
|
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#define | ADC_MR_TRGSEL_ADC_TRIG2 (0x2u << 1) |
| | (ADC_MR) TIO Output of the Timer Counter Channel 1
|
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#define | ADC_MR_TRGSEL_ADC_TRIG3 (0x3u << 1) |
| | (ADC_MR) TIO Output of the Timer Counter Channel 2
|
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#define | ADC_MR_TRGSEL_ADC_TRIG4 (0x4u << 1) |
| | (ADC_MR) PWM Event Line 0
|
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#define | ADC_MR_TRGSEL_ADC_TRIG5 (0x5u << 1) |
| | (ADC_MR) PWM Event Line 1
|
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#define | ADC_MR_LOWRES (0x1u << 4) |
| | (ADC_MR) Resolution
|
| |
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#define | ADC_MR_LOWRES_BITS_12 (0x0u << 4) |
| | (ADC_MR) 12-bit resolution
|
| |
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#define | ADC_MR_LOWRES_BITS_10 (0x1u << 4) |
| | (ADC_MR) 10-bit resolution
|
| |
|
#define | ADC_MR_SLEEP (0x1u << 5) |
| | (ADC_MR) Sleep Mode
|
| |
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#define | ADC_MR_SLEEP_NORMAL (0x0u << 5) |
| | (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions
|
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#define | ADC_MR_SLEEP_SLEEP (0x1u << 5) |
| | (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions
|
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#define | ADC_MR_FWUP (0x1u << 6) |
| | (ADC_MR) Fast Wake Up
|
| |
|
#define | ADC_MR_FWUP_OFF (0x0u << 6) |
| | (ADC_MR) Normal Sleep Mode: The sleep mode is defined by the SLEEP bit
|
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#define | ADC_MR_FWUP_ON (0x1u << 6) |
| | (ADC_MR) Fast Wake Up Sleep Mode: The Voltage reference is ON between conversions and ADC Core is OFF
|
| |
|
#define | ADC_MR_FREERUN (0x1u << 7) |
| | (ADC_MR) Free Run Mode
|
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|
#define | ADC_MR_FREERUN_OFF (0x0u << 7) |
| | (ADC_MR) Normal Mode
|
| |
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#define | ADC_MR_FREERUN_ON (0x1u << 7) |
| | (ADC_MR) Free Run Mode: Never wait for any trigger.
|
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#define | ADC_MR_PRESCAL_Pos 8 |
| |
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#define | ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) |
| | (ADC_MR) Prescaler Rate Selection
|
| |
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#define | ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) |
| |
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#define | ADC_MR_STARTUP_Pos 16 |
| |
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#define | ADC_MR_STARTUP_Msk (0xfu << ADC_MR_STARTUP_Pos) |
| | (ADC_MR) Start Up Time
|
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#define | ADC_MR_STARTUP_SUT0 (0x0u << 16) |
| | (ADC_MR) 0 periods of ADCClock
|
| |
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#define | ADC_MR_STARTUP_SUT8 (0x1u << 16) |
| | (ADC_MR) 8 periods of ADCClock
|
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#define | ADC_MR_STARTUP_SUT16 (0x2u << 16) |
| | (ADC_MR) 16 periods of ADCClock
|
| |
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#define | ADC_MR_STARTUP_SUT24 (0x3u << 16) |
| | (ADC_MR) 24 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT64 (0x4u << 16) |
| | (ADC_MR) 64 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT80 (0x5u << 16) |
| | (ADC_MR) 80 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT96 (0x6u << 16) |
| | (ADC_MR) 96 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT112 (0x7u << 16) |
| | (ADC_MR) 112 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT512 (0x8u << 16) |
| | (ADC_MR) 512 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT576 (0x9u << 16) |
| | (ADC_MR) 576 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT640 (0xAu << 16) |
| | (ADC_MR) 640 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT704 (0xBu << 16) |
| | (ADC_MR) 704 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT768 (0xCu << 16) |
| | (ADC_MR) 768 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT832 (0xDu << 16) |
| | (ADC_MR) 832 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT896 (0xEu << 16) |
| | (ADC_MR) 896 periods of ADCClock
|
| |
|
#define | ADC_MR_STARTUP_SUT960 (0xFu << 16) |
| | (ADC_MR) 960 periods of ADCClock
|
| |
|
#define | ADC_MR_SETTLING_Pos 20 |
| |
|
#define | ADC_MR_SETTLING_Msk (0x3u << ADC_MR_SETTLING_Pos) |
| | (ADC_MR) Analog Settling Time
|
| |
|
#define | ADC_MR_SETTLING_AST3 (0x0u << 20) |
| | (ADC_MR) 3 periods of ADCClock
|
| |
|
#define | ADC_MR_SETTLING_AST5 (0x1u << 20) |
| | (ADC_MR) 5 periods of ADCClock
|
| |
|
#define | ADC_MR_SETTLING_AST9 (0x2u << 20) |
| | (ADC_MR) 9 periods of ADCClock
|
| |
|
#define | ADC_MR_SETTLING_AST17 (0x3u << 20) |
| | (ADC_MR) 17 periods of ADCClock
|
| |
|
#define | ADC_MR_ANACH (0x1u << 23) |
| | (ADC_MR) Analog Change
|
| |
|
#define | ADC_MR_ANACH_NONE (0x0u << 23) |
| | (ADC_MR) No analog change on channel switching: DIFF0, GAIN0 and OFF0 are used for all channels
|
| |
|
#define | ADC_MR_ANACH_ALLOWED (0x1u << 23) |
| | (ADC_MR) Allows different analog settings for each channel. See ADC_CGR and ADC_COR Registers
|
| |
|
#define | ADC_MR_TRACKTIM_Pos 24 |
| |
|
#define | ADC_MR_TRACKTIM_Msk (0xfu << ADC_MR_TRACKTIM_Pos) |
| | (ADC_MR) Tracking Time
|
| |
|
#define | ADC_MR_TRACKTIM(value) ((ADC_MR_TRACKTIM_Msk & ((value) << ADC_MR_TRACKTIM_Pos))) |
| |
|
#define | ADC_MR_TRANSFER_Pos 28 |
| |
|
#define | ADC_MR_TRANSFER_Msk (0x3u << ADC_MR_TRANSFER_Pos) |
| | (ADC_MR) Transfer Period
|
| |
|
#define | ADC_MR_TRANSFER(value) ((ADC_MR_TRANSFER_Msk & ((value) << ADC_MR_TRANSFER_Pos))) |
| |
|
#define | ADC_MR_USEQ (0x1u << 31) |
| | (ADC_MR) Use Sequence Enable
|
| |
|
#define | ADC_MR_USEQ_NUM_ORDER (0x0u << 31) |
| | (ADC_MR) Normal Mode: The controller converts channels in a simple numeric order.
|
| |
|
#define | ADC_MR_USEQ_REG_ORDER (0x1u << 31) |
| | (ADC_MR) User Sequence Mode: The sequence respects what is defined in ADC_SEQR1 and ADC_SEQR2 registers.
|
| |
|
#define | ADC_SEQR1_USCH1_Pos 0 |
| |
|
#define | ADC_SEQR1_USCH1_Msk (0x7u << ADC_SEQR1_USCH1_Pos) |
| | (ADC_SEQR1) User Sequence Number 1
|
| |
|
#define | ADC_SEQR1_USCH1(value) ((ADC_SEQR1_USCH1_Msk & ((value) << ADC_SEQR1_USCH1_Pos))) |
| |
|
#define | ADC_SEQR1_USCH2_Pos 4 |
| |
|
#define | ADC_SEQR1_USCH2_Msk (0x7u << ADC_SEQR1_USCH2_Pos) |
| | (ADC_SEQR1) User Sequence Number 2
|
| |
|
#define | ADC_SEQR1_USCH2(value) ((ADC_SEQR1_USCH2_Msk & ((value) << ADC_SEQR1_USCH2_Pos))) |
| |
|
#define | ADC_SEQR1_USCH3_Pos 8 |
| |
|
#define | ADC_SEQR1_USCH3_Msk (0x7u << ADC_SEQR1_USCH3_Pos) |
| | (ADC_SEQR1) User Sequence Number 3
|
| |
|
#define | ADC_SEQR1_USCH3(value) ((ADC_SEQR1_USCH3_Msk & ((value) << ADC_SEQR1_USCH3_Pos))) |
| |
|
#define | ADC_SEQR1_USCH4_Pos 12 |
| |
|
#define | ADC_SEQR1_USCH4_Msk (0x7u << ADC_SEQR1_USCH4_Pos) |
| | (ADC_SEQR1) User Sequence Number 4
|
| |
|
#define | ADC_SEQR1_USCH4(value) ((ADC_SEQR1_USCH4_Msk & ((value) << ADC_SEQR1_USCH4_Pos))) |
| |
|
#define | ADC_SEQR1_USCH5_Pos 16 |
| |
|
#define | ADC_SEQR1_USCH5_Msk (0x7u << ADC_SEQR1_USCH5_Pos) |
| | (ADC_SEQR1) User Sequence Number 5
|
| |
|
#define | ADC_SEQR1_USCH5(value) ((ADC_SEQR1_USCH5_Msk & ((value) << ADC_SEQR1_USCH5_Pos))) |
| |
|
#define | ADC_SEQR1_USCH6_Pos 20 |
| |
|
#define | ADC_SEQR1_USCH6_Msk (0x7u << ADC_SEQR1_USCH6_Pos) |
| | (ADC_SEQR1) User Sequence Number 6
|
| |
|
#define | ADC_SEQR1_USCH6(value) ((ADC_SEQR1_USCH6_Msk & ((value) << ADC_SEQR1_USCH6_Pos))) |
| |
|
#define | ADC_SEQR1_USCH7_Pos 24 |
| |
|
#define | ADC_SEQR1_USCH7_Msk (0x7u << ADC_SEQR1_USCH7_Pos) |
| | (ADC_SEQR1) User Sequence Number 7
|
| |
|
#define | ADC_SEQR1_USCH7(value) ((ADC_SEQR1_USCH7_Msk & ((value) << ADC_SEQR1_USCH7_Pos))) |
| |
|
#define | ADC_SEQR1_USCH8_Pos 28 |
| |
|
#define | ADC_SEQR1_USCH8_Msk (0x7u << ADC_SEQR1_USCH8_Pos) |
| | (ADC_SEQR1) User Sequence Number 8
|
| |
|
#define | ADC_SEQR1_USCH8(value) ((ADC_SEQR1_USCH8_Msk & ((value) << ADC_SEQR1_USCH8_Pos))) |
| |
|
#define | ADC_SEQR2_USCH9_Pos 0 |
| |
|
#define | ADC_SEQR2_USCH9_Msk (0x7u << ADC_SEQR2_USCH9_Pos) |
| | (ADC_SEQR2) User Sequence Number 9
|
| |
|
#define | ADC_SEQR2_USCH9(value) ((ADC_SEQR2_USCH9_Msk & ((value) << ADC_SEQR2_USCH9_Pos))) |
| |
|
#define | ADC_SEQR2_USCH10_Pos 4 |
| |
|
#define | ADC_SEQR2_USCH10_Msk (0x7u << ADC_SEQR2_USCH10_Pos) |
| | (ADC_SEQR2) User Sequence Number 10
|
| |
|
#define | ADC_SEQR2_USCH10(value) ((ADC_SEQR2_USCH10_Msk & ((value) << ADC_SEQR2_USCH10_Pos))) |
| |
|
#define | ADC_SEQR2_USCH11_Pos 8 |
| |
|
#define | ADC_SEQR2_USCH11_Msk (0x7u << ADC_SEQR2_USCH11_Pos) |
| | (ADC_SEQR2) User Sequence Number 11
|
| |
|
#define | ADC_SEQR2_USCH11(value) ((ADC_SEQR2_USCH11_Msk & ((value) << ADC_SEQR2_USCH11_Pos))) |
| |
|
#define | ADC_SEQR2_USCH12_Pos 12 |
| |
|
#define | ADC_SEQR2_USCH12_Msk (0x7u << ADC_SEQR2_USCH12_Pos) |
| | (ADC_SEQR2) User Sequence Number 12
|
| |
|
#define | ADC_SEQR2_USCH12(value) ((ADC_SEQR2_USCH12_Msk & ((value) << ADC_SEQR2_USCH12_Pos))) |
| |
|
#define | ADC_SEQR2_USCH13_Pos 16 |
| |
|
#define | ADC_SEQR2_USCH13_Msk (0x7u << ADC_SEQR2_USCH13_Pos) |
| | (ADC_SEQR2) User Sequence Number 13
|
| |
|
#define | ADC_SEQR2_USCH13(value) ((ADC_SEQR2_USCH13_Msk & ((value) << ADC_SEQR2_USCH13_Pos))) |
| |
|
#define | ADC_SEQR2_USCH14_Pos 20 |
| |
|
#define | ADC_SEQR2_USCH14_Msk (0x7u << ADC_SEQR2_USCH14_Pos) |
| | (ADC_SEQR2) User Sequence Number 14
|
| |
|
#define | ADC_SEQR2_USCH14(value) ((ADC_SEQR2_USCH14_Msk & ((value) << ADC_SEQR2_USCH14_Pos))) |
| |
|
#define | ADC_SEQR2_USCH15_Pos 24 |
| |
|
#define | ADC_SEQR2_USCH15_Msk (0x7u << ADC_SEQR2_USCH15_Pos) |
| | (ADC_SEQR2) User Sequence Number 15
|
| |
|
#define | ADC_SEQR2_USCH15(value) ((ADC_SEQR2_USCH15_Msk & ((value) << ADC_SEQR2_USCH15_Pos))) |
| |
|
#define | ADC_SEQR2_USCH16_Pos 28 |
| |
|
#define | ADC_SEQR2_USCH16_Msk (0x7u << ADC_SEQR2_USCH16_Pos) |
| | (ADC_SEQR2) User Sequence Number 16
|
| |
|
#define | ADC_SEQR2_USCH16(value) ((ADC_SEQR2_USCH16_Msk & ((value) << ADC_SEQR2_USCH16_Pos))) |
| |
|
#define | ADC_CHER_CH0 (0x1u << 0) |
| | (ADC_CHER) Channel 0 Enable
|
| |
|
#define | ADC_CHER_CH1 (0x1u << 1) |
| | (ADC_CHER) Channel 1 Enable
|
| |
|
#define | ADC_CHER_CH2 (0x1u << 2) |
| | (ADC_CHER) Channel 2 Enable
|
| |
|
#define | ADC_CHER_CH3 (0x1u << 3) |
| | (ADC_CHER) Channel 3 Enable
|
| |
|
#define | ADC_CHER_CH4 (0x1u << 4) |
| | (ADC_CHER) Channel 4 Enable
|
| |
|
#define | ADC_CHER_CH5 (0x1u << 5) |
| | (ADC_CHER) Channel 5 Enable
|
| |
|
#define | ADC_CHER_CH6 (0x1u << 6) |
| | (ADC_CHER) Channel 6 Enable
|
| |
|
#define | ADC_CHER_CH7 (0x1u << 7) |
| | (ADC_CHER) Channel 7 Enable
|
| |
|
#define | ADC_CHER_CH8 (0x1u << 8) |
| | (ADC_CHER) Channel 8 Enable
|
| |
|
#define | ADC_CHER_CH9 (0x1u << 9) |
| | (ADC_CHER) Channel 9 Enable
|
| |
|
#define | ADC_CHER_CH10 (0x1u << 10) |
| | (ADC_CHER) Channel 10 Enable
|
| |
|
#define | ADC_CHER_CH11 (0x1u << 11) |
| | (ADC_CHER) Channel 11 Enable
|
| |
|
#define | ADC_CHER_CH12 (0x1u << 12) |
| | (ADC_CHER) Channel 12 Enable
|
| |
|
#define | ADC_CHER_CH13 (0x1u << 13) |
| | (ADC_CHER) Channel 13 Enable
|
| |
|
#define | ADC_CHER_CH14 (0x1u << 14) |
| | (ADC_CHER) Channel 14 Enable
|
| |
|
#define | ADC_CHER_CH15 (0x1u << 15) |
| | (ADC_CHER) Channel 15 Enable
|
| |
|
#define | ADC_CHDR_CH0 (0x1u << 0) |
| | (ADC_CHDR) Channel 0 Disable
|
| |
|
#define | ADC_CHDR_CH1 (0x1u << 1) |
| | (ADC_CHDR) Channel 1 Disable
|
| |
|
#define | ADC_CHDR_CH2 (0x1u << 2) |
| | (ADC_CHDR) Channel 2 Disable
|
| |
|
#define | ADC_CHDR_CH3 (0x1u << 3) |
| | (ADC_CHDR) Channel 3 Disable
|
| |
|
#define | ADC_CHDR_CH4 (0x1u << 4) |
| | (ADC_CHDR) Channel 4 Disable
|
| |
|
#define | ADC_CHDR_CH5 (0x1u << 5) |
| | (ADC_CHDR) Channel 5 Disable
|
| |
|
#define | ADC_CHDR_CH6 (0x1u << 6) |
| | (ADC_CHDR) Channel 6 Disable
|
| |
|
#define | ADC_CHDR_CH7 (0x1u << 7) |
| | (ADC_CHDR) Channel 7 Disable
|
| |
|
#define | ADC_CHDR_CH8 (0x1u << 8) |
| | (ADC_CHDR) Channel 8 Disable
|
| |
|
#define | ADC_CHDR_CH9 (0x1u << 9) |
| | (ADC_CHDR) Channel 9 Disable
|
| |
|
#define | ADC_CHDR_CH10 (0x1u << 10) |
| | (ADC_CHDR) Channel 10 Disable
|
| |
|
#define | ADC_CHDR_CH11 (0x1u << 11) |
| | (ADC_CHDR) Channel 11 Disable
|
| |
|
#define | ADC_CHDR_CH12 (0x1u << 12) |
| | (ADC_CHDR) Channel 12 Disable
|
| |
|
#define | ADC_CHDR_CH13 (0x1u << 13) |
| | (ADC_CHDR) Channel 13 Disable
|
| |
|
#define | ADC_CHDR_CH14 (0x1u << 14) |
| | (ADC_CHDR) Channel 14 Disable
|
| |
|
#define | ADC_CHDR_CH15 (0x1u << 15) |
| | (ADC_CHDR) Channel 15 Disable
|
| |
|
#define | ADC_CHSR_CH0 (0x1u << 0) |
| | (ADC_CHSR) Channel 0 Status
|
| |
|
#define | ADC_CHSR_CH1 (0x1u << 1) |
| | (ADC_CHSR) Channel 1 Status
|
| |
|
#define | ADC_CHSR_CH2 (0x1u << 2) |
| | (ADC_CHSR) Channel 2 Status
|
| |
|
#define | ADC_CHSR_CH3 (0x1u << 3) |
| | (ADC_CHSR) Channel 3 Status
|
| |
|
#define | ADC_CHSR_CH4 (0x1u << 4) |
| | (ADC_CHSR) Channel 4 Status
|
| |
|
#define | ADC_CHSR_CH5 (0x1u << 5) |
| | (ADC_CHSR) Channel 5 Status
|
| |
|
#define | ADC_CHSR_CH6 (0x1u << 6) |
| | (ADC_CHSR) Channel 6 Status
|
| |
|
#define | ADC_CHSR_CH7 (0x1u << 7) |
| | (ADC_CHSR) Channel 7 Status
|
| |
|
#define | ADC_CHSR_CH8 (0x1u << 8) |
| | (ADC_CHSR) Channel 8 Status
|
| |
|
#define | ADC_CHSR_CH9 (0x1u << 9) |
| | (ADC_CHSR) Channel 9 Status
|
| |
|
#define | ADC_CHSR_CH10 (0x1u << 10) |
| | (ADC_CHSR) Channel 10 Status
|
| |
|
#define | ADC_CHSR_CH11 (0x1u << 11) |
| | (ADC_CHSR) Channel 11 Status
|
| |
|
#define | ADC_CHSR_CH12 (0x1u << 12) |
| | (ADC_CHSR) Channel 12 Status
|
| |
|
#define | ADC_CHSR_CH13 (0x1u << 13) |
| | (ADC_CHSR) Channel 13 Status
|
| |
|
#define | ADC_CHSR_CH14 (0x1u << 14) |
| | (ADC_CHSR) Channel 14 Status
|
| |
|
#define | ADC_CHSR_CH15 (0x1u << 15) |
| | (ADC_CHSR) Channel 15 Status
|
| |
|
#define | ADC_LCDR_LDATA_Pos 0 |
| |
|
#define | ADC_LCDR_LDATA_Msk (0xfffu << ADC_LCDR_LDATA_Pos) |
| | (ADC_LCDR) Last Data Converted
|
| |
|
#define | ADC_LCDR_CHNB_Pos 12 |
| |
|
#define | ADC_LCDR_CHNB_Msk (0xfu << ADC_LCDR_CHNB_Pos) |
| | (ADC_LCDR) Channel Number
|
| |
|
#define | ADC_IER_EOC0 (0x1u << 0) |
| | (ADC_IER) End of Conversion Interrupt Enable 0
|
| |
|
#define | ADC_IER_EOC1 (0x1u << 1) |
| | (ADC_IER) End of Conversion Interrupt Enable 1
|
| |
|
#define | ADC_IER_EOC2 (0x1u << 2) |
| | (ADC_IER) End of Conversion Interrupt Enable 2
|
| |
|
#define | ADC_IER_EOC3 (0x1u << 3) |
| | (ADC_IER) End of Conversion Interrupt Enable 3
|
| |
|
#define | ADC_IER_EOC4 (0x1u << 4) |
| | (ADC_IER) End of Conversion Interrupt Enable 4
|
| |
|
#define | ADC_IER_EOC5 (0x1u << 5) |
| | (ADC_IER) End of Conversion Interrupt Enable 5
|
| |
|
#define | ADC_IER_EOC6 (0x1u << 6) |
| | (ADC_IER) End of Conversion Interrupt Enable 6
|
| |
|
#define | ADC_IER_EOC7 (0x1u << 7) |
| | (ADC_IER) End of Conversion Interrupt Enable 7
|
| |
|
#define | ADC_IER_EOC8 (0x1u << 8) |
| | (ADC_IER) End of Conversion Interrupt Enable 8
|
| |
|
#define | ADC_IER_EOC9 (0x1u << 9) |
| | (ADC_IER) End of Conversion Interrupt Enable 9
|
| |
|
#define | ADC_IER_EOC10 (0x1u << 10) |
| | (ADC_IER) End of Conversion Interrupt Enable 10
|
| |
|
#define | ADC_IER_EOC11 (0x1u << 11) |
| | (ADC_IER) End of Conversion Interrupt Enable 11
|
| |
|
#define | ADC_IER_EOC12 (0x1u << 12) |
| | (ADC_IER) End of Conversion Interrupt Enable 12
|
| |
|
#define | ADC_IER_EOC13 (0x1u << 13) |
| | (ADC_IER) End of Conversion Interrupt Enable 13
|
| |
|
#define | ADC_IER_EOC14 (0x1u << 14) |
| | (ADC_IER) End of Conversion Interrupt Enable 14
|
| |
|
#define | ADC_IER_EOC15 (0x1u << 15) |
| | (ADC_IER) End of Conversion Interrupt Enable 15
|
| |
|
#define | ADC_IER_DRDY (0x1u << 24) |
| | (ADC_IER) Data Ready Interrupt Enable
|
| |
|
#define | ADC_IER_GOVRE (0x1u << 25) |
| | (ADC_IER) General Overrun Error Interrupt Enable
|
| |
|
#define | ADC_IER_COMPE (0x1u << 26) |
| | (ADC_IER) Comparison Event Interrupt Enable
|
| |
|
#define | ADC_IER_ENDRX (0x1u << 27) |
| | (ADC_IER) End of Receive Buffer Interrupt Enable
|
| |
|
#define | ADC_IER_RXBUFF (0x1u << 28) |
| | (ADC_IER) Receive Buffer Full Interrupt Enable
|
| |
|
#define | ADC_IDR_EOC0 (0x1u << 0) |
| | (ADC_IDR) End of Conversion Interrupt Disable 0
|
| |
|
#define | ADC_IDR_EOC1 (0x1u << 1) |
| | (ADC_IDR) End of Conversion Interrupt Disable 1
|
| |
|
#define | ADC_IDR_EOC2 (0x1u << 2) |
| | (ADC_IDR) End of Conversion Interrupt Disable 2
|
| |
|
#define | ADC_IDR_EOC3 (0x1u << 3) |
| | (ADC_IDR) End of Conversion Interrupt Disable 3
|
| |
|
#define | ADC_IDR_EOC4 (0x1u << 4) |
| | (ADC_IDR) End of Conversion Interrupt Disable 4
|
| |
|
#define | ADC_IDR_EOC5 (0x1u << 5) |
| | (ADC_IDR) End of Conversion Interrupt Disable 5
|
| |
|
#define | ADC_IDR_EOC6 (0x1u << 6) |
| | (ADC_IDR) End of Conversion Interrupt Disable 6
|
| |
|
#define | ADC_IDR_EOC7 (0x1u << 7) |
| | (ADC_IDR) End of Conversion Interrupt Disable 7
|
| |
|
#define | ADC_IDR_EOC8 (0x1u << 8) |
| | (ADC_IDR) End of Conversion Interrupt Disable 8
|
| |
|
#define | ADC_IDR_EOC9 (0x1u << 9) |
| | (ADC_IDR) End of Conversion Interrupt Disable 9
|
| |
|
#define | ADC_IDR_EOC10 (0x1u << 10) |
| | (ADC_IDR) End of Conversion Interrupt Disable 10
|
| |
|
#define | ADC_IDR_EOC11 (0x1u << 11) |
| | (ADC_IDR) End of Conversion Interrupt Disable 11
|
| |
|
#define | ADC_IDR_EOC12 (0x1u << 12) |
| | (ADC_IDR) End of Conversion Interrupt Disable 12
|
| |
|
#define | ADC_IDR_EOC13 (0x1u << 13) |
| | (ADC_IDR) End of Conversion Interrupt Disable 13
|
| |
|
#define | ADC_IDR_EOC14 (0x1u << 14) |
| | (ADC_IDR) End of Conversion Interrupt Disable 14
|
| |
|
#define | ADC_IDR_EOC15 (0x1u << 15) |
| | (ADC_IDR) End of Conversion Interrupt Disable 15
|
| |
|
#define | ADC_IDR_DRDY (0x1u << 24) |
| | (ADC_IDR) Data Ready Interrupt Disable
|
| |
|
#define | ADC_IDR_GOVRE (0x1u << 25) |
| | (ADC_IDR) General Overrun Error Interrupt Disable
|
| |
|
#define | ADC_IDR_COMPE (0x1u << 26) |
| | (ADC_IDR) Comparison Event Interrupt Disable
|
| |
|
#define | ADC_IDR_ENDRX (0x1u << 27) |
| | (ADC_IDR) End of Receive Buffer Interrupt Disable
|
| |
|
#define | ADC_IDR_RXBUFF (0x1u << 28) |
| | (ADC_IDR) Receive Buffer Full Interrupt Disable
|
| |
|
#define | ADC_IMR_EOC0 (0x1u << 0) |
| | (ADC_IMR) End of Conversion Interrupt Mask 0
|
| |
|
#define | ADC_IMR_EOC1 (0x1u << 1) |
| | (ADC_IMR) End of Conversion Interrupt Mask 1
|
| |
|
#define | ADC_IMR_EOC2 (0x1u << 2) |
| | (ADC_IMR) End of Conversion Interrupt Mask 2
|
| |
|
#define | ADC_IMR_EOC3 (0x1u << 3) |
| | (ADC_IMR) End of Conversion Interrupt Mask 3
|
| |
|
#define | ADC_IMR_EOC4 (0x1u << 4) |
| | (ADC_IMR) End of Conversion Interrupt Mask 4
|
| |
|
#define | ADC_IMR_EOC5 (0x1u << 5) |
| | (ADC_IMR) End of Conversion Interrupt Mask 5
|
| |
|
#define | ADC_IMR_EOC6 (0x1u << 6) |
| | (ADC_IMR) End of Conversion Interrupt Mask 6
|
| |
|
#define | ADC_IMR_EOC7 (0x1u << 7) |
| | (ADC_IMR) End of Conversion Interrupt Mask 7
|
| |
|
#define | ADC_IMR_EOC8 (0x1u << 8) |
| | (ADC_IMR) End of Conversion Interrupt Mask 8
|
| |
|
#define | ADC_IMR_EOC9 (0x1u << 9) |
| | (ADC_IMR) End of Conversion Interrupt Mask 9
|
| |
|
#define | ADC_IMR_EOC10 (0x1u << 10) |
| | (ADC_IMR) End of Conversion Interrupt Mask 10
|
| |
|
#define | ADC_IMR_EOC11 (0x1u << 11) |
| | (ADC_IMR) End of Conversion Interrupt Mask 11
|
| |
|
#define | ADC_IMR_EOC12 (0x1u << 12) |
| | (ADC_IMR) End of Conversion Interrupt Mask 12
|
| |
|
#define | ADC_IMR_EOC13 (0x1u << 13) |
| | (ADC_IMR) End of Conversion Interrupt Mask 13
|
| |
|
#define | ADC_IMR_EOC14 (0x1u << 14) |
| | (ADC_IMR) End of Conversion Interrupt Mask 14
|
| |
|
#define | ADC_IMR_EOC15 (0x1u << 15) |
| | (ADC_IMR) End of Conversion Interrupt Mask 15
|
| |
|
#define | ADC_IMR_DRDY (0x1u << 24) |
| | (ADC_IMR) Data Ready Interrupt Mask
|
| |
|
#define | ADC_IMR_GOVRE (0x1u << 25) |
| | (ADC_IMR) General Overrun Error Interrupt Mask
|
| |
|
#define | ADC_IMR_COMPE (0x1u << 26) |
| | (ADC_IMR) Comparison Event Interrupt Mask
|
| |
|
#define | ADC_IMR_ENDRX (0x1u << 27) |
| | (ADC_IMR) End of Receive Buffer Interrupt Mask
|
| |
|
#define | ADC_IMR_RXBUFF (0x1u << 28) |
| | (ADC_IMR) Receive Buffer Full Interrupt Mask
|
| |
|
#define | ADC_ISR_EOC0 (0x1u << 0) |
| | (ADC_ISR) End of Conversion 0
|
| |
|
#define | ADC_ISR_EOC1 (0x1u << 1) |
| | (ADC_ISR) End of Conversion 1
|
| |
|
#define | ADC_ISR_EOC2 (0x1u << 2) |
| | (ADC_ISR) End of Conversion 2
|
| |
|
#define | ADC_ISR_EOC3 (0x1u << 3) |
| | (ADC_ISR) End of Conversion 3
|
| |
|
#define | ADC_ISR_EOC4 (0x1u << 4) |
| | (ADC_ISR) End of Conversion 4
|
| |
|
#define | ADC_ISR_EOC5 (0x1u << 5) |
| | (ADC_ISR) End of Conversion 5
|
| |
|
#define | ADC_ISR_EOC6 (0x1u << 6) |
| | (ADC_ISR) End of Conversion 6
|
| |
|
#define | ADC_ISR_EOC7 (0x1u << 7) |
| | (ADC_ISR) End of Conversion 7
|
| |
|
#define | ADC_ISR_EOC8 (0x1u << 8) |
| | (ADC_ISR) End of Conversion 8
|
| |
|
#define | ADC_ISR_EOC9 (0x1u << 9) |
| | (ADC_ISR) End of Conversion 9
|
| |
|
#define | ADC_ISR_EOC10 (0x1u << 10) |
| | (ADC_ISR) End of Conversion 10
|
| |
|
#define | ADC_ISR_EOC11 (0x1u << 11) |
| | (ADC_ISR) End of Conversion 11
|
| |
|
#define | ADC_ISR_EOC12 (0x1u << 12) |
| | (ADC_ISR) End of Conversion 12
|
| |
|
#define | ADC_ISR_EOC13 (0x1u << 13) |
| | (ADC_ISR) End of Conversion 13
|
| |
|
#define | ADC_ISR_EOC14 (0x1u << 14) |
| | (ADC_ISR) End of Conversion 14
|
| |
|
#define | ADC_ISR_EOC15 (0x1u << 15) |
| | (ADC_ISR) End of Conversion 15
|
| |
|
#define | ADC_ISR_DRDY (0x1u << 24) |
| | (ADC_ISR) Data Ready
|
| |
|
#define | ADC_ISR_GOVRE (0x1u << 25) |
| | (ADC_ISR) General Overrun Error
|
| |
|
#define | ADC_ISR_COMPE (0x1u << 26) |
| | (ADC_ISR) Comparison Error
|
| |
|
#define | ADC_ISR_ENDRX (0x1u << 27) |
| | (ADC_ISR) End of RX Buffer
|
| |
|
#define | ADC_ISR_RXBUFF (0x1u << 28) |
| | (ADC_ISR) RX Buffer Full
|
| |
|
#define | ADC_OVER_OVRE0 (0x1u << 0) |
| | (ADC_OVER) Overrun Error 0
|
| |
|
#define | ADC_OVER_OVRE1 (0x1u << 1) |
| | (ADC_OVER) Overrun Error 1
|
| |
|
#define | ADC_OVER_OVRE2 (0x1u << 2) |
| | (ADC_OVER) Overrun Error 2
|
| |
|
#define | ADC_OVER_OVRE3 (0x1u << 3) |
| | (ADC_OVER) Overrun Error 3
|
| |
|
#define | ADC_OVER_OVRE4 (0x1u << 4) |
| | (ADC_OVER) Overrun Error 4
|
| |
|
#define | ADC_OVER_OVRE5 (0x1u << 5) |
| | (ADC_OVER) Overrun Error 5
|
| |
|
#define | ADC_OVER_OVRE6 (0x1u << 6) |
| | (ADC_OVER) Overrun Error 6
|
| |
|
#define | ADC_OVER_OVRE7 (0x1u << 7) |
| | (ADC_OVER) Overrun Error 7
|
| |
|
#define | ADC_OVER_OVRE8 (0x1u << 8) |
| | (ADC_OVER) Overrun Error 8
|
| |
|
#define | ADC_OVER_OVRE9 (0x1u << 9) |
| | (ADC_OVER) Overrun Error 9
|
| |
|
#define | ADC_OVER_OVRE10 (0x1u << 10) |
| | (ADC_OVER) Overrun Error 10
|
| |
|
#define | ADC_OVER_OVRE11 (0x1u << 11) |
| | (ADC_OVER) Overrun Error 11
|
| |
|
#define | ADC_OVER_OVRE12 (0x1u << 12) |
| | (ADC_OVER) Overrun Error 12
|
| |
|
#define | ADC_OVER_OVRE13 (0x1u << 13) |
| | (ADC_OVER) Overrun Error 13
|
| |
|
#define | ADC_OVER_OVRE14 (0x1u << 14) |
| | (ADC_OVER) Overrun Error 14
|
| |
|
#define | ADC_OVER_OVRE15 (0x1u << 15) |
| | (ADC_OVER) Overrun Error 15
|
| |
|
#define | ADC_EMR_CMPMODE_Pos 0 |
| |
|
#define | ADC_EMR_CMPMODE_Msk (0x3u << ADC_EMR_CMPMODE_Pos) |
| | (ADC_EMR) Comparison Mode
|
| |
|
#define | ADC_EMR_CMPMODE_LOW (0x0u << 0) |
| | (ADC_EMR) Generates an event when the converted data is lower than the low threshold of the window.
|
| |
|
#define | ADC_EMR_CMPMODE_HIGH (0x1u << 0) |
| | (ADC_EMR) Generates an event when the converted data is higher than the high threshold of the window.
|
| |
|
#define | ADC_EMR_CMPMODE_IN (0x2u << 0) |
| | (ADC_EMR) Generates an event when the converted data is in the comparison window.
|
| |
|
#define | ADC_EMR_CMPMODE_OUT (0x3u << 0) |
| | (ADC_EMR) Generates an event when the converted data is out of the comparison window.
|
| |
|
#define | ADC_EMR_CMPSEL_Pos 4 |
| |
|
#define | ADC_EMR_CMPSEL_Msk (0xfu << ADC_EMR_CMPSEL_Pos) |
| | (ADC_EMR) Comparison Selected Channel
|
| |
|
#define | ADC_EMR_CMPSEL(value) ((ADC_EMR_CMPSEL_Msk & ((value) << ADC_EMR_CMPSEL_Pos))) |
| |
|
#define | ADC_EMR_CMPALL (0x1u << 9) |
| | (ADC_EMR) Compare All Channels
|
| |
|
#define | ADC_EMR_TAG (0x1u << 24) |
| | (ADC_EMR) TAG of ADC_LDCR register
|
| |
|
#define | ADC_CWR_LOWTHRES_Pos 0 |
| |
|
#define | ADC_CWR_LOWTHRES_Msk (0xfffu << ADC_CWR_LOWTHRES_Pos) |
| | (ADC_CWR) Low Threshold
|
| |
|
#define | ADC_CWR_LOWTHRES(value) ((ADC_CWR_LOWTHRES_Msk & ((value) << ADC_CWR_LOWTHRES_Pos))) |
| |
|
#define | ADC_CWR_HIGHTHRES_Pos 16 |
| |
|
#define | ADC_CWR_HIGHTHRES_Msk (0xfffu << ADC_CWR_HIGHTHRES_Pos) |
| | (ADC_CWR) High Threshold
|
| |
|
#define | ADC_CWR_HIGHTHRES(value) ((ADC_CWR_HIGHTHRES_Msk & ((value) << ADC_CWR_HIGHTHRES_Pos))) |
| |
|
#define | ADC_CGR_GAIN0_Pos 0 |
| |
|
#define | ADC_CGR_GAIN0_Msk (0x3u << ADC_CGR_GAIN0_Pos) |
| | (ADC_CGR) Gain for channel 0
|
| |
|
#define | ADC_CGR_GAIN0(value) ((ADC_CGR_GAIN0_Msk & ((value) << ADC_CGR_GAIN0_Pos))) |
| |
|
#define | ADC_CGR_GAIN1_Pos 2 |
| |
|
#define | ADC_CGR_GAIN1_Msk (0x3u << ADC_CGR_GAIN1_Pos) |
| | (ADC_CGR) Gain for channel 1
|
| |
|
#define | ADC_CGR_GAIN1(value) ((ADC_CGR_GAIN1_Msk & ((value) << ADC_CGR_GAIN1_Pos))) |
| |
|
#define | ADC_CGR_GAIN2_Pos 4 |
| |
|
#define | ADC_CGR_GAIN2_Msk (0x3u << ADC_CGR_GAIN2_Pos) |
| | (ADC_CGR) Gain for channel 2
|
| |
|
#define | ADC_CGR_GAIN2(value) ((ADC_CGR_GAIN2_Msk & ((value) << ADC_CGR_GAIN2_Pos))) |
| |
|
#define | ADC_CGR_GAIN3_Pos 6 |
| |
|
#define | ADC_CGR_GAIN3_Msk (0x3u << ADC_CGR_GAIN3_Pos) |
| | (ADC_CGR) Gain for channel 3
|
| |
|
#define | ADC_CGR_GAIN3(value) ((ADC_CGR_GAIN3_Msk & ((value) << ADC_CGR_GAIN3_Pos))) |
| |
|
#define | ADC_CGR_GAIN4_Pos 8 |
| |
|
#define | ADC_CGR_GAIN4_Msk (0x3u << ADC_CGR_GAIN4_Pos) |
| | (ADC_CGR) Gain for channel 4
|
| |
|
#define | ADC_CGR_GAIN4(value) ((ADC_CGR_GAIN4_Msk & ((value) << ADC_CGR_GAIN4_Pos))) |
| |
|
#define | ADC_CGR_GAIN5_Pos 10 |
| |
|
#define | ADC_CGR_GAIN5_Msk (0x3u << ADC_CGR_GAIN5_Pos) |
| | (ADC_CGR) Gain for channel 5
|
| |
|
#define | ADC_CGR_GAIN5(value) ((ADC_CGR_GAIN5_Msk & ((value) << ADC_CGR_GAIN5_Pos))) |
| |
|
#define | ADC_CGR_GAIN6_Pos 12 |
| |
|
#define | ADC_CGR_GAIN6_Msk (0x3u << ADC_CGR_GAIN6_Pos) |
| | (ADC_CGR) Gain for channel 6
|
| |
|
#define | ADC_CGR_GAIN6(value) ((ADC_CGR_GAIN6_Msk & ((value) << ADC_CGR_GAIN6_Pos))) |
| |
|
#define | ADC_CGR_GAIN7_Pos 14 |
| |
|
#define | ADC_CGR_GAIN7_Msk (0x3u << ADC_CGR_GAIN7_Pos) |
| | (ADC_CGR) Gain for channel 7
|
| |
|
#define | ADC_CGR_GAIN7(value) ((ADC_CGR_GAIN7_Msk & ((value) << ADC_CGR_GAIN7_Pos))) |
| |
|
#define | ADC_CGR_GAIN8_Pos 16 |
| |
|
#define | ADC_CGR_GAIN8_Msk (0x3u << ADC_CGR_GAIN8_Pos) |
| | (ADC_CGR) Gain for channel 8
|
| |
|
#define | ADC_CGR_GAIN8(value) ((ADC_CGR_GAIN8_Msk & ((value) << ADC_CGR_GAIN8_Pos))) |
| |
|
#define | ADC_CGR_GAIN9_Pos 18 |
| |
|
#define | ADC_CGR_GAIN9_Msk (0x3u << ADC_CGR_GAIN9_Pos) |
| | (ADC_CGR) Gain for channel 9
|
| |
|
#define | ADC_CGR_GAIN9(value) ((ADC_CGR_GAIN9_Msk & ((value) << ADC_CGR_GAIN9_Pos))) |
| |
|
#define | ADC_CGR_GAIN10_Pos 20 |
| |
|
#define | ADC_CGR_GAIN10_Msk (0x3u << ADC_CGR_GAIN10_Pos) |
| | (ADC_CGR) Gain for channel 10
|
| |
|
#define | ADC_CGR_GAIN10(value) ((ADC_CGR_GAIN10_Msk & ((value) << ADC_CGR_GAIN10_Pos))) |
| |
|
#define | ADC_CGR_GAIN11_Pos 22 |
| |
|
#define | ADC_CGR_GAIN11_Msk (0x3u << ADC_CGR_GAIN11_Pos) |
| | (ADC_CGR) Gain for channel 11
|
| |
|
#define | ADC_CGR_GAIN11(value) ((ADC_CGR_GAIN11_Msk & ((value) << ADC_CGR_GAIN11_Pos))) |
| |
|
#define | ADC_CGR_GAIN12_Pos 24 |
| |
|
#define | ADC_CGR_GAIN12_Msk (0x3u << ADC_CGR_GAIN12_Pos) |
| | (ADC_CGR) Gain for channel 12
|
| |
|
#define | ADC_CGR_GAIN12(value) ((ADC_CGR_GAIN12_Msk & ((value) << ADC_CGR_GAIN12_Pos))) |
| |
|
#define | ADC_CGR_GAIN13_Pos 26 |
| |
|
#define | ADC_CGR_GAIN13_Msk (0x3u << ADC_CGR_GAIN13_Pos) |
| | (ADC_CGR) Gain for channel 13
|
| |
|
#define | ADC_CGR_GAIN13(value) ((ADC_CGR_GAIN13_Msk & ((value) << ADC_CGR_GAIN13_Pos))) |
| |
|
#define | ADC_CGR_GAIN14_Pos 28 |
| |
|
#define | ADC_CGR_GAIN14_Msk (0x3u << ADC_CGR_GAIN14_Pos) |
| | (ADC_CGR) Gain for channel 14
|
| |
|
#define | ADC_CGR_GAIN14(value) ((ADC_CGR_GAIN14_Msk & ((value) << ADC_CGR_GAIN14_Pos))) |
| |
|
#define | ADC_CGR_GAIN15_Pos 30 |
| |
|
#define | ADC_CGR_GAIN15_Msk (0x3u << ADC_CGR_GAIN15_Pos) |
| | (ADC_CGR) Gain for channel 15
|
| |
|
#define | ADC_CGR_GAIN15(value) ((ADC_CGR_GAIN15_Msk & ((value) << ADC_CGR_GAIN15_Pos))) |
| |
|
#define | ADC_COR_OFF0 (0x1u << 0) |
| | (ADC_COR) Offset for channel 0
|
| |
|
#define | ADC_COR_OFF1 (0x1u << 1) |
| | (ADC_COR) Offset for channel 1
|
| |
|
#define | ADC_COR_OFF2 (0x1u << 2) |
| | (ADC_COR) Offset for channel 2
|
| |
|
#define | ADC_COR_OFF3 (0x1u << 3) |
| | (ADC_COR) Offset for channel 3
|
| |
|
#define | ADC_COR_OFF4 (0x1u << 4) |
| | (ADC_COR) Offset for channel 4
|
| |
|
#define | ADC_COR_OFF5 (0x1u << 5) |
| | (ADC_COR) Offset for channel 5
|
| |
|
#define | ADC_COR_OFF6 (0x1u << 6) |
| | (ADC_COR) Offset for channel 6
|
| |
|
#define | ADC_COR_OFF7 (0x1u << 7) |
| | (ADC_COR) Offset for channel 7
|
| |
|
#define | ADC_COR_OFF8 (0x1u << 8) |
| | (ADC_COR) Offset for channel 8
|
| |
|
#define | ADC_COR_OFF9 (0x1u << 9) |
| | (ADC_COR) Offset for channel 9
|
| |
|
#define | ADC_COR_OFF10 (0x1u << 10) |
| | (ADC_COR) Offset for channel 10
|
| |
|
#define | ADC_COR_OFF11 (0x1u << 11) |
| | (ADC_COR) Offset for channel 11
|
| |
|
#define | ADC_COR_OFF12 (0x1u << 12) |
| | (ADC_COR) Offset for channel 12
|
| |
|
#define | ADC_COR_OFF13 (0x1u << 13) |
| | (ADC_COR) Offset for channel 13
|
| |
|
#define | ADC_COR_OFF14 (0x1u << 14) |
| | (ADC_COR) Offset for channel 14
|
| |
|
#define | ADC_COR_OFF15 (0x1u << 15) |
| | (ADC_COR) Offset for channel 15
|
| |
|
#define | ADC_COR_DIFF0 (0x1u << 16) |
| | (ADC_COR) Differential inputs for channel 0
|
| |
|
#define | ADC_COR_DIFF1 (0x1u << 17) |
| | (ADC_COR) Differential inputs for channel 1
|
| |
|
#define | ADC_COR_DIFF2 (0x1u << 18) |
| | (ADC_COR) Differential inputs for channel 2
|
| |
|
#define | ADC_COR_DIFF3 (0x1u << 19) |
| | (ADC_COR) Differential inputs for channel 3
|
| |
|
#define | ADC_COR_DIFF4 (0x1u << 20) |
| | (ADC_COR) Differential inputs for channel 4
|
| |
|
#define | ADC_COR_DIFF5 (0x1u << 21) |
| | (ADC_COR) Differential inputs for channel 5
|
| |
|
#define | ADC_COR_DIFF6 (0x1u << 22) |
| | (ADC_COR) Differential inputs for channel 6
|
| |
|
#define | ADC_COR_DIFF7 (0x1u << 23) |
| | (ADC_COR) Differential inputs for channel 7
|
| |
|
#define | ADC_COR_DIFF8 (0x1u << 24) |
| | (ADC_COR) Differential inputs for channel 8
|
| |
|
#define | ADC_COR_DIFF9 (0x1u << 25) |
| | (ADC_COR) Differential inputs for channel 9
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#define | ADC_COR_DIFF10 (0x1u << 26) |
| | (ADC_COR) Differential inputs for channel 10
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#define | ADC_COR_DIFF11 (0x1u << 27) |
| | (ADC_COR) Differential inputs for channel 11
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#define | ADC_COR_DIFF12 (0x1u << 28) |
| | (ADC_COR) Differential inputs for channel 12
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#define | ADC_COR_DIFF13 (0x1u << 29) |
| | (ADC_COR) Differential inputs for channel 13
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#define | ADC_COR_DIFF14 (0x1u << 30) |
| | (ADC_COR) Differential inputs for channel 14
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#define | ADC_COR_DIFF15 (0x1u << 31) |
| | (ADC_COR) Differential inputs for channel 15
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#define | ADC_CDR_DATA_Pos 0 |
| |
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#define | ADC_CDR_DATA_Msk (0xfffu << ADC_CDR_DATA_Pos) |
| | (ADC_CDR[15]) Converted Data
|
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#define | ADC_ACR_TSON (0x1u << 4) |
| | (ADC_ACR) Temperature Sensor On
|
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#define | ADC_ACR_IBCTL_Pos 8 |
| |
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#define | ADC_ACR_IBCTL_Msk (0x3u << ADC_ACR_IBCTL_Pos) |
| | (ADC_ACR) ADC Bias Current Control
|
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#define | ADC_ACR_IBCTL(value) ((ADC_ACR_IBCTL_Msk & ((value) << ADC_ACR_IBCTL_Pos))) |
| |
|
#define | ADC_WPMR_WPEN (0x1u << 0) |
| | (ADC_WPMR) Write Protect Enable
|
| |
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#define | ADC_WPMR_WPKEY_Pos 8 |
| |
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#define | ADC_WPMR_WPKEY_Msk (0xffffffu << ADC_WPMR_WPKEY_Pos) |
| | (ADC_WPMR) Write Protect KEY
|
| |
|
#define | ADC_WPMR_WPKEY(value) ((ADC_WPMR_WPKEY_Msk & ((value) << ADC_WPMR_WPKEY_Pos))) |
| |
|
#define | ADC_WPSR_WPVS (0x1u << 0) |
| | (ADC_WPSR) Write Protect Violation Status
|
| |
|
#define | ADC_WPSR_WPVSRC_Pos 8 |
| |
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#define | ADC_WPSR_WPVSRC_Msk (0xffffu << ADC_WPSR_WPVSRC_Pos) |
| | (ADC_WPSR) Write Protect Violation Source
|
| |
|
#define | ADC_RPR_RXPTR_Pos 0 |
| |
|
#define | ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) |
| | (ADC_RPR) Receive Pointer Register
|
| |
|
#define | ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) |
| |
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#define | ADC_RCR_RXCTR_Pos 0 |
| |
|
#define | ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) |
| | (ADC_RCR) Receive Counter Register
|
| |
|
#define | ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) |
| |
|
#define | ADC_RNPR_RXNPTR_Pos 0 |
| |
|
#define | ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) |
| | (ADC_RNPR) Receive Next Pointer
|
| |
|
#define | ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) |
| |
|
#define | ADC_RNCR_RXNCTR_Pos 0 |
| |
|
#define | ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) |
| | (ADC_RNCR) Receive Next Counter
|
| |
|
#define | ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) |
| |
|
#define | ADC_PTCR_RXTEN (0x1u << 0) |
| | (ADC_PTCR) Receiver Transfer Enable
|
| |
|
#define | ADC_PTCR_RXTDIS (0x1u << 1) |
| | (ADC_PTCR) Receiver Transfer Disable
|
| |
|
#define | ADC_PTCR_TXTEN (0x1u << 8) |
| | (ADC_PTCR) Transmitter Transfer Enable
|
| |
|
#define | ADC_PTCR_TXTDIS (0x1u << 9) |
| | (ADC_PTCR) Transmitter Transfer Disable
|
| |
|
#define | ADC_PTSR_RXTEN (0x1u << 0) |
| | (ADC_PTSR) Receiver Transfer Enable
|
| |
|
#define | ADC_PTSR_TXTEN (0x1u << 8) |
| | (ADC_PTSR) Transmitter Transfer Enable
|
| |
1.8.11 
