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#define | ADC_CR_SWRST (0x1u << 0) |
| | (ADC_CR) Software Reset
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#define | ADC_CR_START (0x1u << 1) |
| | (ADC_CR) Start Conversion
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#define | ADC_MR_TRGEN (0x1u << 0) |
| | (ADC_MR) Trigger Enable
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#define | ADC_MR_TRGEN_DIS (0x0u << 0) |
| | (ADC_MR) Hardware triggers are disabled. Starting a conversion is only possible by software.
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#define | ADC_MR_TRGEN_EN (0x1u << 0) |
| | (ADC_MR) Hardware trigger selected by TRGSEL field is enabled.
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#define | ADC_MR_TRGSEL_Pos 1 |
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#define | ADC_MR_TRGSEL_Msk (0x7u << ADC_MR_TRGSEL_Pos) |
| | (ADC_MR) Trigger Selection
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#define | ADC_MR_TRGSEL(value) ((ADC_MR_TRGSEL_Msk & ((value) << ADC_MR_TRGSEL_Pos))) |
| |
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#define | ADC_MR_TRGSEL_ADC_TRIG0 (0x6u << 1) |
| | (ADC_MR) External trigger
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#define | ADC_MR_TRGSEL_ADC_TRIG1 (0x0u << 1) |
| | (ADC_MR) TIO Output of the Timer Counter Channel 0
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#define | ADC_MR_TRGSEL_ADC_TRIG2 (0x1u << 1) |
| | (ADC_MR) TIO Output of the Timer Counter Channel 1
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#define | ADC_MR_TRGSEL_ADC_TRIG3 (0x2u << 1) |
| | (ADC_MR) TIO Output of the Timer Counter Channel 2
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#define | ADC_MR_TRGSEL_ADC_TRIG4 (0x3u << 1) |
| | (ADC_MR) PWM Event Line 0
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#define | ADC_MR_TRGSEL_ADC_TRIG5 (0x4u << 1) |
| | (ADC_MR) PWM Event Line 1
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#define | ADC_MR_LOWRES (0x1u << 4) |
| | (ADC_MR) Resolution
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#define | ADC_MR_LOWRES_BITS_10 (0x0u << 4) |
| | (ADC_MR) 10-bit resolution
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#define | ADC_MR_LOWRES_BITS_8 (0x1u << 4) |
| | (ADC_MR) 8-bit resolution
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#define | ADC_MR_SLEEP (0x1u << 5) |
| | (ADC_MR) Sleep Mode
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#define | ADC_MR_SLEEP_NORMAL (0x0u << 5) |
| | (ADC_MR) Normal Mode: The ADC Core and reference voltage circuitry are kept ON between conversions
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#define | ADC_MR_SLEEP_SLEEP (0x1u << 5) |
| | (ADC_MR) Sleep Mode: The ADC Core and reference voltage circuitry are OFF between conversions
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#define | ADC_MR_PRESCAL_Pos 8 |
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#define | ADC_MR_PRESCAL_Msk (0xffu << ADC_MR_PRESCAL_Pos) |
| | (ADC_MR) Prescaler Rate Selection
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#define | ADC_MR_PRESCAL(value) ((ADC_MR_PRESCAL_Msk & ((value) << ADC_MR_PRESCAL_Pos))) |
| |
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#define | ADC_MR_STARTUP_Pos 16 |
| |
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#define | ADC_MR_STARTUP_Msk (0x7fu << ADC_MR_STARTUP_Pos) |
| | (ADC_MR) Start Up Time
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#define | ADC_MR_STARTUP(value) ((ADC_MR_STARTUP_Msk & ((value) << ADC_MR_STARTUP_Pos))) |
| |
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#define | ADC_MR_SHTIM_Pos 24 |
| |
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#define | ADC_MR_SHTIM_Msk (0xfu << ADC_MR_SHTIM_Pos) |
| | (ADC_MR) Sample & Hold Time
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#define | ADC_MR_SHTIM(value) ((ADC_MR_SHTIM_Msk & ((value) << ADC_MR_SHTIM_Pos))) |
| |
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#define | ADC_CHER_CH0 (0x1u << 0) |
| | (ADC_CHER) Channel 0 Enable
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#define | ADC_CHER_CH1 (0x1u << 1) |
| | (ADC_CHER) Channel 1 Enable
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#define | ADC_CHER_CH2 (0x1u << 2) |
| | (ADC_CHER) Channel 2 Enable
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#define | ADC_CHER_CH3 (0x1u << 3) |
| | (ADC_CHER) Channel 3 Enable
|
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#define | ADC_CHER_CH4 (0x1u << 4) |
| | (ADC_CHER) Channel 4 Enable
|
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#define | ADC_CHER_CH5 (0x1u << 5) |
| | (ADC_CHER) Channel 5 Enable
|
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#define | ADC_CHER_CH6 (0x1u << 6) |
| | (ADC_CHER) Channel 6 Enable
|
| |
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#define | ADC_CHER_CH7 (0x1u << 7) |
| | (ADC_CHER) Channel 7 Enable
|
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#define | ADC_CHDR_CH0 (0x1u << 0) |
| | (ADC_CHDR) Channel 0 Disable
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#define | ADC_CHDR_CH1 (0x1u << 1) |
| | (ADC_CHDR) Channel 1 Disable
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#define | ADC_CHDR_CH2 (0x1u << 2) |
| | (ADC_CHDR) Channel 2 Disable
|
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#define | ADC_CHDR_CH3 (0x1u << 3) |
| | (ADC_CHDR) Channel 3 Disable
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#define | ADC_CHDR_CH4 (0x1u << 4) |
| | (ADC_CHDR) Channel 4 Disable
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#define | ADC_CHDR_CH5 (0x1u << 5) |
| | (ADC_CHDR) Channel 5 Disable
|
| |
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#define | ADC_CHDR_CH6 (0x1u << 6) |
| | (ADC_CHDR) Channel 6 Disable
|
| |
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#define | ADC_CHDR_CH7 (0x1u << 7) |
| | (ADC_CHDR) Channel 7 Disable
|
| |
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#define | ADC_CHSR_CH0 (0x1u << 0) |
| | (ADC_CHSR) Channel 0 Status
|
| |
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#define | ADC_CHSR_CH1 (0x1u << 1) |
| | (ADC_CHSR) Channel 1 Status
|
| |
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#define | ADC_CHSR_CH2 (0x1u << 2) |
| | (ADC_CHSR) Channel 2 Status
|
| |
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#define | ADC_CHSR_CH3 (0x1u << 3) |
| | (ADC_CHSR) Channel 3 Status
|
| |
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#define | ADC_CHSR_CH4 (0x1u << 4) |
| | (ADC_CHSR) Channel 4 Status
|
| |
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#define | ADC_CHSR_CH5 (0x1u << 5) |
| | (ADC_CHSR) Channel 5 Status
|
| |
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#define | ADC_CHSR_CH6 (0x1u << 6) |
| | (ADC_CHSR) Channel 6 Status
|
| |
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#define | ADC_CHSR_CH7 (0x1u << 7) |
| | (ADC_CHSR) Channel 7 Status
|
| |
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#define | ADC_SR_EOC0 (0x1u << 0) |
| | (ADC_SR) End of Conversion 0
|
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#define | ADC_SR_EOC1 (0x1u << 1) |
| | (ADC_SR) End of Conversion 1
|
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#define | ADC_SR_EOC2 (0x1u << 2) |
| | (ADC_SR) End of Conversion 2
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| |
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#define | ADC_SR_EOC3 (0x1u << 3) |
| | (ADC_SR) End of Conversion 3
|
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#define | ADC_SR_EOC4 (0x1u << 4) |
| | (ADC_SR) End of Conversion 4
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#define | ADC_SR_EOC5 (0x1u << 5) |
| | (ADC_SR) End of Conversion 5
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| |
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#define | ADC_SR_EOC6 (0x1u << 6) |
| | (ADC_SR) End of Conversion 6
|
| |
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#define | ADC_SR_EOC7 (0x1u << 7) |
| | (ADC_SR) End of Conversion 7
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| |
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#define | ADC_SR_OVRE0 (0x1u << 8) |
| | (ADC_SR) Overrun Error 0
|
| |
|
#define | ADC_SR_OVRE1 (0x1u << 9) |
| | (ADC_SR) Overrun Error 1
|
| |
|
#define | ADC_SR_OVRE2 (0x1u << 10) |
| | (ADC_SR) Overrun Error 2
|
| |
|
#define | ADC_SR_OVRE3 (0x1u << 11) |
| | (ADC_SR) Overrun Error 3
|
| |
|
#define | ADC_SR_OVRE4 (0x1u << 12) |
| | (ADC_SR) Overrun Error 4
|
| |
|
#define | ADC_SR_OVRE5 (0x1u << 13) |
| | (ADC_SR) Overrun Error 5
|
| |
|
#define | ADC_SR_OVRE6 (0x1u << 14) |
| | (ADC_SR) Overrun Error 6
|
| |
|
#define | ADC_SR_OVRE7 (0x1u << 15) |
| | (ADC_SR) Overrun Error 7
|
| |
|
#define | ADC_SR_DRDY (0x1u << 16) |
| | (ADC_SR) Data Ready
|
| |
|
#define | ADC_SR_GOVRE (0x1u << 17) |
| | (ADC_SR) General Overrun Error
|
| |
|
#define | ADC_SR_ENDRX (0x1u << 18) |
| | (ADC_SR) End of RX Buffer
|
| |
|
#define | ADC_SR_RXBUFF (0x1u << 19) |
| | (ADC_SR) RX Buffer Full
|
| |
|
#define | ADC_LCDR_LDATA_Pos 0 |
| |
|
#define | ADC_LCDR_LDATA_Msk (0x3ffu << ADC_LCDR_LDATA_Pos) |
| | (ADC_LCDR) Last Data Converted
|
| |
|
#define | ADC_IER_EOC0 (0x1u << 0) |
| | (ADC_IER) End of Conversion Interrupt Enable 0
|
| |
|
#define | ADC_IER_EOC1 (0x1u << 1) |
| | (ADC_IER) End of Conversion Interrupt Enable 1
|
| |
|
#define | ADC_IER_EOC2 (0x1u << 2) |
| | (ADC_IER) End of Conversion Interrupt Enable 2
|
| |
|
#define | ADC_IER_EOC3 (0x1u << 3) |
| | (ADC_IER) End of Conversion Interrupt Enable 3
|
| |
|
#define | ADC_IER_EOC4 (0x1u << 4) |
| | (ADC_IER) End of Conversion Interrupt Enable 4
|
| |
|
#define | ADC_IER_EOC5 (0x1u << 5) |
| | (ADC_IER) End of Conversion Interrupt Enable 5
|
| |
|
#define | ADC_IER_EOC6 (0x1u << 6) |
| | (ADC_IER) End of Conversion Interrupt Enable 6
|
| |
|
#define | ADC_IER_EOC7 (0x1u << 7) |
| | (ADC_IER) End of Conversion Interrupt Enable 7
|
| |
|
#define | ADC_IER_OVRE0 (0x1u << 8) |
| | (ADC_IER) Overrun Error Interrupt Enable 0
|
| |
|
#define | ADC_IER_OVRE1 (0x1u << 9) |
| | (ADC_IER) Overrun Error Interrupt Enable 1
|
| |
|
#define | ADC_IER_OVRE2 (0x1u << 10) |
| | (ADC_IER) Overrun Error Interrupt Enable 2
|
| |
|
#define | ADC_IER_OVRE3 (0x1u << 11) |
| | (ADC_IER) Overrun Error Interrupt Enable 3
|
| |
|
#define | ADC_IER_OVRE4 (0x1u << 12) |
| | (ADC_IER) Overrun Error Interrupt Enable 4
|
| |
|
#define | ADC_IER_OVRE5 (0x1u << 13) |
| | (ADC_IER) Overrun Error Interrupt Enable 5
|
| |
|
#define | ADC_IER_OVRE6 (0x1u << 14) |
| | (ADC_IER) Overrun Error Interrupt Enable 6
|
| |
|
#define | ADC_IER_OVRE7 (0x1u << 15) |
| | (ADC_IER) Overrun Error Interrupt Enable 7
|
| |
|
#define | ADC_IER_DRDY (0x1u << 16) |
| | (ADC_IER) Data Ready Interrupt Enable
|
| |
|
#define | ADC_IER_GOVRE (0x1u << 17) |
| | (ADC_IER) General Overrun Error Interrupt Enable
|
| |
|
#define | ADC_IER_ENDRX (0x1u << 18) |
| | (ADC_IER) End of Receive Buffer Interrupt Enable
|
| |
|
#define | ADC_IER_RXBUFF (0x1u << 19) |
| | (ADC_IER) Receive Buffer Full Interrupt Enable
|
| |
|
#define | ADC_IDR_EOC0 (0x1u << 0) |
| | (ADC_IDR) End of Conversion Interrupt Disable 0
|
| |
|
#define | ADC_IDR_EOC1 (0x1u << 1) |
| | (ADC_IDR) End of Conversion Interrupt Disable 1
|
| |
|
#define | ADC_IDR_EOC2 (0x1u << 2) |
| | (ADC_IDR) End of Conversion Interrupt Disable 2
|
| |
|
#define | ADC_IDR_EOC3 (0x1u << 3) |
| | (ADC_IDR) End of Conversion Interrupt Disable 3
|
| |
|
#define | ADC_IDR_EOC4 (0x1u << 4) |
| | (ADC_IDR) End of Conversion Interrupt Disable 4
|
| |
|
#define | ADC_IDR_EOC5 (0x1u << 5) |
| | (ADC_IDR) End of Conversion Interrupt Disable 5
|
| |
|
#define | ADC_IDR_EOC6 (0x1u << 6) |
| | (ADC_IDR) End of Conversion Interrupt Disable 6
|
| |
|
#define | ADC_IDR_EOC7 (0x1u << 7) |
| | (ADC_IDR) End of Conversion Interrupt Disable 7
|
| |
|
#define | ADC_IDR_OVRE0 (0x1u << 8) |
| | (ADC_IDR) Overrun Error Interrupt Disable 0
|
| |
|
#define | ADC_IDR_OVRE1 (0x1u << 9) |
| | (ADC_IDR) Overrun Error Interrupt Disable 1
|
| |
|
#define | ADC_IDR_OVRE2 (0x1u << 10) |
| | (ADC_IDR) Overrun Error Interrupt Disable 2
|
| |
|
#define | ADC_IDR_OVRE3 (0x1u << 11) |
| | (ADC_IDR) Overrun Error Interrupt Disable 3
|
| |
|
#define | ADC_IDR_OVRE4 (0x1u << 12) |
| | (ADC_IDR) Overrun Error Interrupt Disable 4
|
| |
|
#define | ADC_IDR_OVRE5 (0x1u << 13) |
| | (ADC_IDR) Overrun Error Interrupt Disable 5
|
| |
|
#define | ADC_IDR_OVRE6 (0x1u << 14) |
| | (ADC_IDR) Overrun Error Interrupt Disable 6
|
| |
|
#define | ADC_IDR_OVRE7 (0x1u << 15) |
| | (ADC_IDR) Overrun Error Interrupt Disable 7
|
| |
|
#define | ADC_IDR_DRDY (0x1u << 16) |
| | (ADC_IDR) Data Ready Interrupt Disable
|
| |
|
#define | ADC_IDR_GOVRE (0x1u << 17) |
| | (ADC_IDR) General Overrun Error Interrupt Disable
|
| |
|
#define | ADC_IDR_ENDRX (0x1u << 18) |
| | (ADC_IDR) End of Receive Buffer Interrupt Disable
|
| |
|
#define | ADC_IDR_RXBUFF (0x1u << 19) |
| | (ADC_IDR) Receive Buffer Full Interrupt Disable
|
| |
|
#define | ADC_IMR_EOC0 (0x1u << 0) |
| | (ADC_IMR) End of Conversion Interrupt Mask 0
|
| |
|
#define | ADC_IMR_EOC1 (0x1u << 1) |
| | (ADC_IMR) End of Conversion Interrupt Mask 1
|
| |
|
#define | ADC_IMR_EOC2 (0x1u << 2) |
| | (ADC_IMR) End of Conversion Interrupt Mask 2
|
| |
|
#define | ADC_IMR_EOC3 (0x1u << 3) |
| | (ADC_IMR) End of Conversion Interrupt Mask 3
|
| |
|
#define | ADC_IMR_EOC4 (0x1u << 4) |
| | (ADC_IMR) End of Conversion Interrupt Mask 4
|
| |
|
#define | ADC_IMR_EOC5 (0x1u << 5) |
| | (ADC_IMR) End of Conversion Interrupt Mask 5
|
| |
|
#define | ADC_IMR_EOC6 (0x1u << 6) |
| | (ADC_IMR) End of Conversion Interrupt Mask 6
|
| |
|
#define | ADC_IMR_EOC7 (0x1u << 7) |
| | (ADC_IMR) End of Conversion Interrupt Mask 7
|
| |
|
#define | ADC_IMR_OVRE0 (0x1u << 8) |
| | (ADC_IMR) Overrun Error Interrupt Mask 0
|
| |
|
#define | ADC_IMR_OVRE1 (0x1u << 9) |
| | (ADC_IMR) Overrun Error Interrupt Mask 1
|
| |
|
#define | ADC_IMR_OVRE2 (0x1u << 10) |
| | (ADC_IMR) Overrun Error Interrupt Mask 2
|
| |
|
#define | ADC_IMR_OVRE3 (0x1u << 11) |
| | (ADC_IMR) Overrun Error Interrupt Mask 3
|
| |
|
#define | ADC_IMR_OVRE4 (0x1u << 12) |
| | (ADC_IMR) Overrun Error Interrupt Mask 4
|
| |
|
#define | ADC_IMR_OVRE5 (0x1u << 13) |
| | (ADC_IMR) Overrun Error Interrupt Mask 5
|
| |
|
#define | ADC_IMR_OVRE6 (0x1u << 14) |
| | (ADC_IMR) Overrun Error Interrupt Mask 6
|
| |
|
#define | ADC_IMR_OVRE7 (0x1u << 15) |
| | (ADC_IMR) Overrun Error Interrupt Mask 7
|
| |
|
#define | ADC_IMR_DRDY (0x1u << 16) |
| | (ADC_IMR) Data Ready Interrupt Mask
|
| |
|
#define | ADC_IMR_GOVRE (0x1u << 17) |
| | (ADC_IMR) General Overrun Error Interrupt Mask
|
| |
|
#define | ADC_IMR_ENDRX (0x1u << 18) |
| | (ADC_IMR) End of Receive Buffer Interrupt Mask
|
| |
|
#define | ADC_IMR_RXBUFF (0x1u << 19) |
| | (ADC_IMR) Receive Buffer Full Interrupt Mask
|
| |
|
#define | ADC_CDR_DATA_Pos 0 |
| |
|
#define | ADC_CDR_DATA_Msk (0x3ffu << ADC_CDR_DATA_Pos) |
| | (ADC_CDR[8]) Converted Data
|
| |
|
#define | ADC_RPR_RXPTR_Pos 0 |
| |
|
#define | ADC_RPR_RXPTR_Msk (0xffffffffu << ADC_RPR_RXPTR_Pos) |
| | (ADC_RPR) Receive Pointer Register
|
| |
|
#define | ADC_RPR_RXPTR(value) ((ADC_RPR_RXPTR_Msk & ((value) << ADC_RPR_RXPTR_Pos))) |
| |
|
#define | ADC_RCR_RXCTR_Pos 0 |
| |
|
#define | ADC_RCR_RXCTR_Msk (0xffffu << ADC_RCR_RXCTR_Pos) |
| | (ADC_RCR) Receive Counter Register
|
| |
|
#define | ADC_RCR_RXCTR(value) ((ADC_RCR_RXCTR_Msk & ((value) << ADC_RCR_RXCTR_Pos))) |
| |
|
#define | ADC_RNPR_RXNPTR_Pos 0 |
| |
|
#define | ADC_RNPR_RXNPTR_Msk (0xffffffffu << ADC_RNPR_RXNPTR_Pos) |
| | (ADC_RNPR) Receive Next Pointer
|
| |
|
#define | ADC_RNPR_RXNPTR(value) ((ADC_RNPR_RXNPTR_Msk & ((value) << ADC_RNPR_RXNPTR_Pos))) |
| |
|
#define | ADC_RNCR_RXNCTR_Pos 0 |
| |
|
#define | ADC_RNCR_RXNCTR_Msk (0xffffu << ADC_RNCR_RXNCTR_Pos) |
| | (ADC_RNCR) Receive Next Counter
|
| |
|
#define | ADC_RNCR_RXNCTR(value) ((ADC_RNCR_RXNCTR_Msk & ((value) << ADC_RNCR_RXNCTR_Pos))) |
| |
|
#define | ADC_PTCR_RXTEN (0x1u << 0) |
| | (ADC_PTCR) Receiver Transfer Enable
|
| |
|
#define | ADC_PTCR_RXTDIS (0x1u << 1) |
| | (ADC_PTCR) Receiver Transfer Disable
|
| |
|
#define | ADC_PTCR_TXTEN (0x1u << 8) |
| | (ADC_PTCR) Transmitter Transfer Enable
|
| |
|
#define | ADC_PTCR_TXTDIS (0x1u << 9) |
| | (ADC_PTCR) Transmitter Transfer Disable
|
| |
|
#define | ADC_PTSR_RXTEN (0x1u << 0) |
| | (ADC_PTSR) Receiver Transfer Enable
|
| |
|
#define | ADC_PTSR_TXTEN (0x1u << 8) |
| | (ADC_PTSR) Transmitter Transfer Enable
|
| |
1.8.11 
