Public Attributes
RwReg	PWM_MR
	(Pwm Offset: 0x00) PWM Mode Register

WoReg	PWM_ENA
	(Pwm Offset: 0x04) PWM Enable Register

WoReg	PWM_DIS
	(Pwm Offset: 0x08) PWM Disable Register

RoReg	PWM_SR
	(Pwm Offset: 0x0C) PWM Status Register

WoReg	PWM_IER
	(Pwm Offset: 0x10) PWM Interrupt Enable Register

WoReg	PWM_IDR
	(Pwm Offset: 0x14) PWM Interrupt Disable Register

RoReg	PWM_IMR
	(Pwm Offset: 0x18) PWM Interrupt Mask Register

RoReg	PWM_ISR
	(Pwm Offset: 0x1C) PWM Interrupt Status Register

RoReg	Reserved1 [120]

PwmCh_num	PWM_CH_NUM [PWMCH_NUM_NUMBER]
	(Pwm Offset: 0x200) ch_num = 0 .. 3 More...

RwReg	PWM_CLK
	(Pwm Offset: 0x00) PWM Clock Register

WoReg	PWM_IER1
	(Pwm Offset: 0x10) PWM Interrupt Enable Register 1

WoReg	PWM_IDR1
	(Pwm Offset: 0x14) PWM Interrupt Disable Register 1

RoReg	PWM_IMR1
	(Pwm Offset: 0x18) PWM Interrupt Mask Register 1

RoReg	PWM_ISR1
	(Pwm Offset: 0x1C) PWM Interrupt Status Register 1

RwReg	PWM_SCM
	(Pwm Offset: 0x20) PWM Sync Channels Mode Register

RwReg	PWM_SCUC
	(Pwm Offset: 0x28) PWM Sync Channels Update Control Register

RwReg	PWM_SCUP
	(Pwm Offset: 0x2C) PWM Sync Channels Update Period Register

WoReg	PWM_SCUPUPD
	(Pwm Offset: 0x30) PWM Sync Channels Update Period Update Register

WoReg	PWM_IER2
	(Pwm Offset: 0x34) PWM Interrupt Enable Register 2

WoReg	PWM_IDR2
	(Pwm Offset: 0x38) PWM Interrupt Disable Register 2

RoReg	PWM_IMR2
	(Pwm Offset: 0x3C) PWM Interrupt Mask Register 2

RoReg	PWM_ISR2
	(Pwm Offset: 0x40) PWM Interrupt Status Register 2

RwReg	PWM_OOV
	(Pwm Offset: 0x44) PWM Output Override Value Register

RwReg	PWM_OS
	(Pwm Offset: 0x48) PWM Output Selection Register

WoReg	PWM_OSS
	(Pwm Offset: 0x4C) PWM Output Selection Set Register

WoReg	PWM_OSC
	(Pwm Offset: 0x50) PWM Output Selection Clear Register

WoReg	PWM_OSSUPD
	(Pwm Offset: 0x54) PWM Output Selection Set Update Register

WoReg	PWM_OSCUPD
	(Pwm Offset: 0x58) PWM Output Selection Clear Update Register

RwReg	PWM_FMR
	(Pwm Offset: 0x5C) PWM Fault Mode Register

RoReg	PWM_FSR
	(Pwm Offset: 0x60) PWM Fault Status Register

WoReg	PWM_FCR
	(Pwm Offset: 0x64) PWM Fault Clear Register

RwReg	PWM_FPV
	(Pwm Offset: 0x68) PWM Fault Protection Value Register

RwReg	PWM_FPE
	(Pwm Offset: 0x6C) PWM Fault Protection Enable Register

RoReg	Reserved2 [3]

RwReg	PWM_ELMR [2]
	(Pwm Offset: 0x7C) PWM Event Line 0 Mode Register

RoReg	Reserved3 [11]

RwReg	PWM_SMMR
	(Pwm Offset: 0xB0) PWM Stepper Motor Mode Register

RoReg	Reserved4 [12]

WoReg	PWM_WPCR
	(Pwm Offset: 0xE4) PWM Write Protect Control Register

RoReg	PWM_WPSR
	(Pwm Offset: 0xE8) PWM Write Protect Status Register

RoReg	Reserved5 [7]

RwReg	PWM_TPR
	(Pwm Offset: 0x108) Transmit Pointer Register

RwReg	PWM_TCR
	(Pwm Offset: 0x10C) Transmit Counter Register

RoReg	Reserved6 [2]

RwReg	PWM_TNPR
	(Pwm Offset: 0x118) Transmit Next Pointer Register

RwReg	PWM_TNCR
	(Pwm Offset: 0x11C) Transmit Next Counter Register

WoReg	PWM_PTCR
	(Pwm Offset: 0x120) Transfer Control Register

RoReg	PWM_PTSR
	(Pwm Offset: 0x124) Transfer Status Register

RoReg	Reserved7 [2]

PwmCmp	PWM_CMP [PWMCMP_NUMBER]
	(Pwm Offset: 0x130) 0 .. 7

RoReg	Reserved8 [20]

RwReg	PWM_FPE1
	(Pwm Offset: 0x6C) PWM Fault Protection Enable Register 1

RwReg	PWM_FPE2
	(Pwm Offset: 0x70) PWM Fault Protection Enable Register 2

Member Data Documentation

PwmCh_num Pwm::PWM_CH_NUM

(Pwm Offset: 0x200) ch_num = 0 .. 3

(Pwm Offset: 0x200) ch_num = 0 .. 7

The documentation for this struct was generated from the following file:

src/CMSIS/Device/ATMEL/sam3n/include/component/component_pwm.h

Public Attributes

Member Data Documentation