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Pulse Width Modulation Controller

Classes

struct  PwmCh_num
 PwmCh_num hardware registers. More...
 
struct  Pwm
 

Macros

#define PWMCH_NUM_NUMBER   4
 Pwm hardware registers.
 
#define PWM_MR_DIVA_Pos   0
 
#define PWM_MR_DIVA_Msk   (0xffu << PWM_MR_DIVA_Pos)
 (PWM_MR) CLKA, CLKB Divide Factor
 
#define PWM_MR_DIVA_CLK_OFF   (0x0u << 0)
 (PWM_MR) CLKA, CLKB clock is turned off
 
#define PWM_MR_DIVA_CLK_DIV1   (0x1u << 0)
 (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB
 
#define PWM_MR_PREA_Pos   8
 
#define PWM_MR_PREA_Msk   (0xfu << PWM_MR_PREA_Pos)
 (PWM_MR)
 
#define PWM_MR_PREA_MCK   (0x0u << 8)
 (PWM_MR) Master Clock
 
#define PWM_MR_PREA_MCKDIV2   (0x1u << 8)
 (PWM_MR) Master Clock divided by 2
 
#define PWM_MR_PREA_MCKDIV4   (0x2u << 8)
 (PWM_MR) Master Clock divided by 4
 
#define PWM_MR_PREA_MCKDIV8   (0x3u << 8)
 (PWM_MR) Master Clock divided by 8
 
#define PWM_MR_PREA_MCKDIV16   (0x4u << 8)
 (PWM_MR) Master Clock divided by 16
 
#define PWM_MR_PREA_MCKDIV32   (0x5u << 8)
 (PWM_MR) Master Clock divided by 32
 
#define PWM_MR_PREA_MCKDIV64   (0x6u << 8)
 (PWM_MR) Master Clock divided by 64
 
#define PWM_MR_PREA_MCKDIV128   (0x7u << 8)
 (PWM_MR) Master Clock divided by 128
 
#define PWM_MR_PREA_MCKDIV256   (0x8u << 8)
 (PWM_MR) Master Clock divided by 256
 
#define PWM_MR_PREA_MCKDIV512   (0x9u << 8)
 (PWM_MR) Master Clock divided by 512
 
#define PWM_MR_PREA_MCKDIV1024   (0xAu << 8)
 (PWM_MR) Master Clock divided by 1024
 
#define PWM_MR_DIVB_Pos   16
 
#define PWM_MR_DIVB_Msk   (0xffu << PWM_MR_DIVB_Pos)
 (PWM_MR) CLKA, CLKB Divide Factor
 
#define PWM_MR_DIVB_CLK_OFF   (0x0u << 16)
 (PWM_MR) CLKA, CLKB clock is turned off
 
#define PWM_MR_DIVB_CLK_DIV1   (0x1u << 16)
 (PWM_MR) CLKA, CLKB clock is clock selected by PREA, PREB
 
#define PWM_MR_PREB_Pos   24
 
#define PWM_MR_PREB_Msk   (0xfu << PWM_MR_PREB_Pos)
 (PWM_MR)
 
#define PWM_MR_PREB_MCK   (0x0u << 24)
 (PWM_MR) Master Clock
 
#define PWM_MR_PREB_MCKDIV2   (0x1u << 24)
 (PWM_MR) Master Clock divided by 2
 
#define PWM_MR_PREB_MCKDIV4   (0x2u << 24)
 (PWM_MR) Master Clock divided by 4
 
#define PWM_MR_PREB_MCKDIV8   (0x3u << 24)
 (PWM_MR) Master Clock divided by 8
 
#define PWM_MR_PREB_MCKDIV16   (0x4u << 24)
 (PWM_MR) Master Clock divided by 16
 
#define PWM_MR_PREB_MCKDIV32   (0x5u << 24)
 (PWM_MR) Master Clock divided by 32
 
#define PWM_MR_PREB_MCKDIV64   (0x6u << 24)
 (PWM_MR) Master Clock divided by 64
 
#define PWM_MR_PREB_MCKDIV128   (0x7u << 24)
 (PWM_MR) Master Clock divided by 128
 
#define PWM_MR_PREB_MCKDIV256   (0x8u << 24)
 (PWM_MR) Master Clock divided by 256
 
#define PWM_MR_PREB_MCKDIV512   (0x9u << 24)
 (PWM_MR) Master Clock divided by 512
 
#define PWM_MR_PREB_MCKDIV1024   (0xAu << 24)
 (PWM_MR) Master Clock divided by 1024
 
#define PWM_ENA_CHID0   (0x1u << 0)
 (PWM_ENA) Channel ID
 
#define PWM_ENA_CHID1   (0x1u << 1)
 (PWM_ENA) Channel ID
 
#define PWM_ENA_CHID2   (0x1u << 2)
 (PWM_ENA) Channel ID
 
#define PWM_ENA_CHID3   (0x1u << 3)
 (PWM_ENA) Channel ID
 
#define PWM_DIS_CHID0   (0x1u << 0)
 (PWM_DIS) Channel ID
 
#define PWM_DIS_CHID1   (0x1u << 1)
 (PWM_DIS) Channel ID
 
#define PWM_DIS_CHID2   (0x1u << 2)
 (PWM_DIS) Channel ID
 
#define PWM_DIS_CHID3   (0x1u << 3)
 (PWM_DIS) Channel ID
 
#define PWM_SR_CHID0   (0x1u << 0)
 (PWM_SR) Channel ID
 
#define PWM_SR_CHID1   (0x1u << 1)
 (PWM_SR) Channel ID
 
#define PWM_SR_CHID2   (0x1u << 2)
 (PWM_SR) Channel ID
 
#define PWM_SR_CHID3   (0x1u << 3)
 (PWM_SR) Channel ID
 
#define PWM_IER_CHID0   (0x1u << 0)
 (PWM_IER) Channel ID.
 
#define PWM_IER_CHID1   (0x1u << 1)
 (PWM_IER) Channel ID.
 
#define PWM_IER_CHID2   (0x1u << 2)
 (PWM_IER) Channel ID.
 
#define PWM_IER_CHID3   (0x1u << 3)
 (PWM_IER) Channel ID.
 
#define PWM_IDR_CHID0   (0x1u << 0)
 (PWM_IDR) Channel ID.
 
#define PWM_IDR_CHID1   (0x1u << 1)
 (PWM_IDR) Channel ID.
 
#define PWM_IDR_CHID2   (0x1u << 2)
 (PWM_IDR) Channel ID.
 
#define PWM_IDR_CHID3   (0x1u << 3)
 (PWM_IDR) Channel ID.
 
#define PWM_IMR_CHID0   (0x1u << 0)
 (PWM_IMR) Channel ID.
 
#define PWM_IMR_CHID1   (0x1u << 1)
 (PWM_IMR) Channel ID.
 
#define PWM_IMR_CHID2   (0x1u << 2)
 (PWM_IMR) Channel ID.
 
#define PWM_IMR_CHID3   (0x1u << 3)
 (PWM_IMR) Channel ID.
 
#define PWM_ISR_CHID0   (0x1u << 0)
 (PWM_ISR) Channel ID
 
#define PWM_ISR_CHID1   (0x1u << 1)
 (PWM_ISR) Channel ID
 
#define PWM_ISR_CHID2   (0x1u << 2)
 (PWM_ISR) Channel ID
 
#define PWM_ISR_CHID3   (0x1u << 3)
 (PWM_ISR) Channel ID
 
#define PWM_CMR_CPRE_Pos   0
 
#define PWM_CMR_CPRE_Msk   (0xfu << PWM_CMR_CPRE_Pos)
 (PWM_CMR) Channel Pre-scaler
 
#define PWM_CMR_CPRE_MCK   (0x0u << 0)
 (PWM_CMR) Master Clock
 
#define PWM_CMR_CPRE_MCKDIV2   (0x1u << 0)
 (PWM_CMR) Master Clock divided by 2
 
#define PWM_CMR_CPRE_MCKDIV4   (0x2u << 0)
 (PWM_CMR) Master Clock divided by 4
 
#define PWM_CMR_CPRE_MCKDIV8   (0x3u << 0)
 (PWM_CMR) Master Clock divided by 8
 
#define PWM_CMR_CPRE_MCKDIV16   (0x4u << 0)
 (PWM_CMR) Master Clock divided by 16
 
#define PWM_CMR_CPRE_MCKDIV32   (0x5u << 0)
 (PWM_CMR) Master Clock divided by 32
 
#define PWM_CMR_CPRE_MCKDIV64   (0x6u << 0)
 (PWM_CMR) Master Clock divided by 64
 
#define PWM_CMR_CPRE_MCKDIV128   (0x7u << 0)
 (PWM_CMR) Master Clock divided by 128
 
#define PWM_CMR_CPRE_MCKDIV256   (0x8u << 0)
 (PWM_CMR) Master Clock divided by 256
 
#define PWM_CMR_CPRE_MCKDIV512   (0x9u << 0)
 (PWM_CMR) Master Clock divided by 512
 
#define PWM_CMR_CPRE_MCKDIV1024   (0xAu << 0)
 (PWM_CMR) Master Clock divided by 1024
 
#define PWM_CMR_CPRE_CLKA   (0xBu << 0)
 (PWM_CMR) Clock A
 
#define PWM_CMR_CPRE_CLKB   (0xCu << 0)
 (PWM_CMR) Clock B
 
#define PWM_CMR_CALG   (0x1u << 8)
 (PWM_CMR) Channel Alignment
 
#define PWM_CMR_CPOL   (0x1u << 9)
 (PWM_CMR) Channel Polarity
 
#define PWM_CMR_CPD   (0x1u << 10)
 (PWM_CMR) Channel Update Period
 
#define PWM_CDTY_CDTY_Pos   0
 
#define PWM_CDTY_CDTY_Msk   (0xffffffffu << PWM_CDTY_CDTY_Pos)
 (PWM_CDTY) Channel Duty Cycle
 
#define PWM_CDTY_CDTY(value)   ((PWM_CDTY_CDTY_Msk & ((value) << PWM_CDTY_CDTY_Pos)))
 
#define PWM_CPRD_CPRD_Pos   0
 
#define PWM_CPRD_CPRD_Msk   (0xffffffffu << PWM_CPRD_CPRD_Pos)
 (PWM_CPRD) Channel Period
 
#define PWM_CPRD_CPRD(value)   ((PWM_CPRD_CPRD_Msk & ((value) << PWM_CPRD_CPRD_Pos)))
 
#define PWM_CCNT_CNT_Pos   0
 
#define PWM_CCNT_CNT_Msk   (0xffffffffu << PWM_CCNT_CNT_Pos)
 (PWM_CCNT) Channel Counter Register
 
#define PWM_CUPD_CUPD_Pos   0
 
#define PWM_CUPD_CUPD_Msk   (0xffffffffu << PWM_CUPD_CUPD_Pos)
 (PWM_CUPD)
 
#define PWM_CUPD_CUPD(value)   ((PWM_CUPD_CUPD_Msk & ((value) << PWM_CUPD_CUPD_Pos)))
 

Detailed Description

SOFTWARE API DEFINITION FOR Pulse Width Modulation Controller