robobo/doxygen/a00482_source.html

 /**************************************************************************/
 #if defined ( __ICCARM__ )
  #pragma system_include  /* treat file as system include file for MISRA check */
 #endif

 #ifdef __cplusplus
  extern "C" {
 #endif

 #ifndef __CORE_CM3_H_GENERIC
 #define __CORE_CM3_H_GENERIC


 /*******************************************************************************
  *                 CMSIS definitions
  ******************************************************************************/
 /*  CMSIS CM3 definitions */
 #define __CM3_CMSIS_VERSION_MAIN  (0x02)
 #define __CM3_CMSIS_VERSION_SUB   (0x10)
 #define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB)
 #define __CORTEX_M                (0x03)
 #if   defined ( __CC_ARM )
   #define __ASM            __asm
   #define __INLINE         __inline
 #elif defined ( __ICCARM__ )
   #define __ASM           __asm
   #define __INLINE        inline
 #elif defined ( __GNUC__ )
   #define __ASM            __asm
   #define __INLINE         inline
 #elif defined ( __TASKING__ )
   #define __ASM            __asm
   #define __INLINE         inline
 #endif


 #define __FPU_USED       0
 #if defined ( __CC_ARM )
   #if defined __TARGET_FPU_VFP
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif
 #elif defined ( __ICCARM__ )
   #if defined __ARMVFP__
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif

 #elif defined ( __GNUC__ )
   #if defined (__VFP_FP__) && !defined(__SOFTFP__)
     #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
   #endif

 #elif defined ( __TASKING__ )
     /* add preprocessor checks */
 #endif

 #include <stdint.h>
 #include "core_cmInstr.h"
 #include "core_cmFunc.h"
 #endif /* __CORE_CM3_H_GENERIC */

 #ifndef __CMSIS_GENERIC

 #ifndef __CORE_CM3_H_DEPENDANT
 #define __CORE_CM3_H_DEPENDANT

 /* check device defines and use defaults */
 #if defined __CHECK_DEVICE_DEFINES
   #ifndef __CM3_REV
     #define __CM3_REV               0x0200
     #warning "__CM3_REV not defined in device header file; using default!"
   #endif

   #ifndef __MPU_PRESENT
     #define __MPU_PRESENT             0
     #warning "__MPU_PRESENT not defined in device header file; using default!"
   #endif

   #ifndef __NVIC_PRIO_BITS
     #define __NVIC_PRIO_BITS          4
     #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
   #endif

   #ifndef __Vendor_SysTickConfig
     #define __Vendor_SysTickConfig    0
     #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
   #endif
 #endif

 /* IO definitions (access restrictions to peripheral registers) */
 #ifdef __cplusplus
   #define   __I     volatile
 #else
   #define   __I     volatile const
 #endif
 #define     __O     volatile
 #define     __IO    volatile

 /*******************************************************************************
  *                 Register Abstraction
  ******************************************************************************/

 typedef union
 {
   struct
   {
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:27;
 #else
     uint32_t _reserved0:16;
     uint32_t GE:4;
     uint32_t _reserved1:7;
 #endif
     uint32_t Q:1;
     uint32_t V:1;
     uint32_t C:1;
     uint32_t Z:1;
     uint32_t N:1;
   } b;
   uint32_t w;
 } APSR_Type;


 typedef union
 {
   struct
   {
     uint32_t ISR:9;
     uint32_t _reserved0:23;
   } b;
   uint32_t w;
 } IPSR_Type;


 typedef union
 {
   struct
   {
     uint32_t ISR:9;
 #if (__CORTEX_M != 0x04)
     uint32_t _reserved0:15;
 #else
     uint32_t _reserved0:7;
     uint32_t GE:4;
     uint32_t _reserved1:4;
 #endif
     uint32_t T:1;
     uint32_t IT:2;
     uint32_t Q:1;
     uint32_t V:1;
     uint32_t C:1;
     uint32_t Z:1;
     uint32_t N:1;
   } b;
   uint32_t w;
 } xPSR_Type;


 typedef union
 {
   struct
   {
     uint32_t nPRIV:1;
     uint32_t SPSEL:1;
     uint32_t FPCA:1;
     uint32_t _reserved0:29;
   } b;
   uint32_t w;
 } CONTROL_Type;

 typedef struct
 {
   __IO uint32_t ISER[8];
        uint32_t RESERVED0[24];
   __IO uint32_t ICER[8];
        uint32_t RSERVED1[24];
   __IO uint32_t ISPR[8];
        uint32_t RESERVED2[24];
   __IO uint32_t ICPR[8];
        uint32_t RESERVED3[24];
   __IO uint32_t IABR[8];
        uint32_t RESERVED4[56];
   __IO uint8_t  IP[240];
        uint32_t RESERVED5[644];
   __O  uint32_t STIR;
 }  NVIC_Type;

 /* Software Triggered Interrupt Register Definitions */
 #define NVIC_STIR_INTID_Pos                 0
 #define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)

 typedef struct
 {
   __I  uint32_t CPUID;
   __IO uint32_t ICSR;
   __IO uint32_t VTOR;
   __IO uint32_t AIRCR;
   __IO uint32_t SCR;
   __IO uint32_t CCR;
   __IO uint8_t  SHP[12];
   __IO uint32_t SHCSR;
   __IO uint32_t CFSR;
   __IO uint32_t HFSR;
   __IO uint32_t DFSR;
   __IO uint32_t MMFAR;
   __IO uint32_t BFAR;
   __IO uint32_t AFSR;
   __I  uint32_t PFR[2];
   __I  uint32_t DFR;
   __I  uint32_t ADR;
   __I  uint32_t MMFR[4];
   __I  uint32_t ISAR[5];
        uint32_t RESERVED0[5];
   __IO uint32_t CPACR;
 } SCB_Type;

 /* SCB CPUID Register Definitions */
 #define SCB_CPUID_IMPLEMENTER_Pos          24
 #define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)
 #define SCB_CPUID_VARIANT_Pos              20
 #define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)
 #define SCB_CPUID_ARCHITECTURE_Pos         16
 #define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)
 #define SCB_CPUID_PARTNO_Pos                4
 #define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)
 #define SCB_CPUID_REVISION_Pos              0
 #define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)
 /* SCB Interrupt Control State Register Definitions */
 #define SCB_ICSR_NMIPENDSET_Pos            31
 #define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)
 #define SCB_ICSR_PENDSVSET_Pos             28
 #define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)
 #define SCB_ICSR_PENDSVCLR_Pos             27
 #define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)
 #define SCB_ICSR_PENDSTSET_Pos             26
 #define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)
 #define SCB_ICSR_PENDSTCLR_Pos             25
 #define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)
 #define SCB_ICSR_ISRPREEMPT_Pos            23
 #define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)
 #define SCB_ICSR_ISRPENDING_Pos            22
 #define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)
 #define SCB_ICSR_VECTPENDING_Pos           12
 #define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)
 #define SCB_ICSR_RETTOBASE_Pos             11
 #define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)
 #define SCB_ICSR_VECTACTIVE_Pos             0
 #define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)
 /* SCB Vector Table Offset Register Definitions */
 #if (__CM3_REV < 0x0201)                   /* core r2p1 */
 #define SCB_VTOR_TBLBASE_Pos               29
 #define SCB_VTOR_TBLBASE_Msk               (1UL << SCB_VTOR_TBLBASE_Pos)
 #define SCB_VTOR_TBLOFF_Pos                 7
 #define SCB_VTOR_TBLOFF_Msk                (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos)
 #else
 #define SCB_VTOR_TBLOFF_Pos                 7
 #define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)
 #endif

 /* SCB Application Interrupt and Reset Control Register Definitions */
 #define SCB_AIRCR_VECTKEY_Pos              16
 #define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)
 #define SCB_AIRCR_VECTKEYSTAT_Pos          16
 #define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)
 #define SCB_AIRCR_ENDIANESS_Pos            15
 #define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)
 #define SCB_AIRCR_PRIGROUP_Pos              8
 #define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)
 #define SCB_AIRCR_SYSRESETREQ_Pos           2
 #define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)
 #define SCB_AIRCR_VECTCLRACTIVE_Pos         1
 #define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)
 #define SCB_AIRCR_VECTRESET_Pos             0
 #define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)
 /* SCB System Control Register Definitions */
 #define SCB_SCR_SEVONPEND_Pos               4
 #define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)
 #define SCB_SCR_SLEEPDEEP_Pos               2
 #define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)
 #define SCB_SCR_SLEEPONEXIT_Pos             1
 #define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)
 /* SCB Configuration Control Register Definitions */
 #define SCB_CCR_STKALIGN_Pos                9
 #define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)
 #define SCB_CCR_BFHFNMIGN_Pos               8
 #define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)
 #define SCB_CCR_DIV_0_TRP_Pos               4
 #define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)
 #define SCB_CCR_UNALIGN_TRP_Pos             3
 #define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)
 #define SCB_CCR_USERSETMPEND_Pos            1
 #define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)
 #define SCB_CCR_NONBASETHRDENA_Pos          0
 #define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)
 /* SCB System Handler Control and State Register Definitions */
 #define SCB_SHCSR_USGFAULTENA_Pos          18
 #define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)
 #define SCB_SHCSR_BUSFAULTENA_Pos          17
 #define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)
 #define SCB_SHCSR_MEMFAULTENA_Pos          16
 #define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)
 #define SCB_SHCSR_SVCALLPENDED_Pos         15
 #define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)
 #define SCB_SHCSR_BUSFAULTPENDED_Pos       14
 #define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)
 #define SCB_SHCSR_MEMFAULTPENDED_Pos       13
 #define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)
 #define SCB_SHCSR_USGFAULTPENDED_Pos       12
 #define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)
 #define SCB_SHCSR_SYSTICKACT_Pos           11
 #define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)
 #define SCB_SHCSR_PENDSVACT_Pos            10
 #define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)
 #define SCB_SHCSR_MONITORACT_Pos            8
 #define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)
 #define SCB_SHCSR_SVCALLACT_Pos             7
 #define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)
 #define SCB_SHCSR_USGFAULTACT_Pos           3
 #define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)
 #define SCB_SHCSR_BUSFAULTACT_Pos           1
 #define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)
 #define SCB_SHCSR_MEMFAULTACT_Pos           0
 #define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)
 /* SCB Configurable Fault Status Registers Definitions */
 #define SCB_CFSR_USGFAULTSR_Pos            16
 #define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)
 #define SCB_CFSR_BUSFAULTSR_Pos             8
 #define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)
 #define SCB_CFSR_MEMFAULTSR_Pos             0
 #define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)
 /* SCB Hard Fault Status Registers Definitions */
 #define SCB_HFSR_DEBUGEVT_Pos              31
 #define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)
 #define SCB_HFSR_FORCED_Pos                30
 #define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)
 #define SCB_HFSR_VECTTBL_Pos                1
 #define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)
 /* SCB Debug Fault Status Register Definitions */
 #define SCB_DFSR_EXTERNAL_Pos               4
 #define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)
 #define SCB_DFSR_VCATCH_Pos                 3
 #define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)
 #define SCB_DFSR_DWTTRAP_Pos                2
 #define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)
 #define SCB_DFSR_BKPT_Pos                   1
 #define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)
 #define SCB_DFSR_HALTED_Pos                 0
 #define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)

 typedef struct
 {
        uint32_t RESERVED0[1];
   __I  uint32_t ICTR;
 #if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
   __IO uint32_t ACTLR;
 #else
        uint32_t RESERVED1[1];
 #endif
 } SCnSCB_Type;

 /* Interrupt Controller Type Register Definitions */
 #define SCnSCB_ICTR_INTLINESNUM_Pos         0
 #define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)
 /* Auxiliary Control Register Definitions */

 #define SCnSCB_ACTLR_DISFOLD_Pos            2
 #define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)
 #define SCnSCB_ACTLR_DISDEFWBUF_Pos         1
 #define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)
 #define SCnSCB_ACTLR_DISMCYCINT_Pos         0
 #define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)

 typedef struct
 {
   __IO uint32_t CTRL;
   __IO uint32_t LOAD;
   __IO uint32_t VAL;
   __I  uint32_t CALIB;
 } SysTick_Type;

 /* SysTick Control / Status Register Definitions */
 #define SysTick_CTRL_COUNTFLAG_Pos         16
 #define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)
 #define SysTick_CTRL_CLKSOURCE_Pos          2
 #define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)
 #define SysTick_CTRL_TICKINT_Pos            1
 #define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)
 #define SysTick_CTRL_ENABLE_Pos             0
 #define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)
 /* SysTick Reload Register Definitions */
 #define SysTick_LOAD_RELOAD_Pos             0
 #define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)
 /* SysTick Current Register Definitions */
 #define SysTick_VAL_CURRENT_Pos             0
 #define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)
 /* SysTick Calibration Register Definitions */
 #define SysTick_CALIB_NOREF_Pos            31
 #define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)
 #define SysTick_CALIB_SKEW_Pos             30
 #define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)
 #define SysTick_CALIB_TENMS_Pos             0
 #define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)

 typedef struct
 {
   __O  union
   {
     __O  uint8_t    u8;
     __O  uint16_t   u16;
     __O  uint32_t   u32;
   }  PORT [32];
        uint32_t RESERVED0[864];
   __IO uint32_t TER;
        uint32_t RESERVED1[15];
   __IO uint32_t TPR;
        uint32_t RESERVED2[15];
   __IO uint32_t TCR;
 } ITM_Type;

 /* ITM Trace Privilege Register Definitions */
 #define ITM_TPR_PRIVMASK_Pos                0
 #define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)
 /* ITM Trace Control Register Definitions */
 #define ITM_TCR_BUSY_Pos                   23
 #define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)
 #define ITM_TCR_TraceBusID_Pos             16
 #define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)
 #define ITM_TCR_GTSFREQ_Pos                10
 #define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)
 #define ITM_TCR_TSPrescale_Pos              8
 #define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)
 #define ITM_TCR_SWOENA_Pos                  4
 #define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)
 #define ITM_TCR_TXENA_Pos                   3
 #define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)
 #define ITM_TCR_SYNCENA_Pos                 2
 #define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)
 #define ITM_TCR_TSENA_Pos                   1
 #define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)
 #define ITM_TCR_ITMENA_Pos                  0
 #define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)
  /* end of group CMSIS_ITM */


 #if (__MPU_PRESENT == 1)

 typedef struct
 {
   __I  uint32_t TYPE;
   __IO uint32_t CTRL;
   __IO uint32_t RNR;
   __IO uint32_t RBAR;
   __IO uint32_t RASR;
   __IO uint32_t RBAR_A1;
   __IO uint32_t RASR_A1;
   __IO uint32_t RBAR_A2;
   __IO uint32_t RASR_A2;
   __IO uint32_t RBAR_A3;
   __IO uint32_t RASR_A3;
 } MPU_Type;

 /* MPU Type Register */
 #define MPU_TYPE_IREGION_Pos               16
 #define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)
 #define MPU_TYPE_DREGION_Pos                8
 #define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)
 #define MPU_TYPE_SEPARATE_Pos               0
 #define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)
 /* MPU Control Register */
 #define MPU_CTRL_PRIVDEFENA_Pos             2
 #define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)
 #define MPU_CTRL_HFNMIENA_Pos               1
 #define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)
 #define MPU_CTRL_ENABLE_Pos                 0
 #define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)
 /* MPU Region Number Register */
 #define MPU_RNR_REGION_Pos                  0
 #define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)
 /* MPU Region Base Address Register */
 #define MPU_RBAR_ADDR_Pos                   5
 #define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)
 #define MPU_RBAR_VALID_Pos                  4
 #define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)
 #define MPU_RBAR_REGION_Pos                 0
 #define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)
 /* MPU Region Attribute and Size Register */
 #define MPU_RASR_ATTRS_Pos                 16
 #define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)
 #define MPU_RASR_SRD_Pos                    8
 #define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)
 #define MPU_RASR_SIZE_Pos                   1
 #define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)
 #define MPU_RASR_ENABLE_Pos                 0
 #define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)

 #endif


 typedef struct
 {
   __IO uint32_t DHCSR;
   __O  uint32_t DCRSR;
   __IO uint32_t DCRDR;
   __IO uint32_t DEMCR;
 } CoreDebug_Type;

 /* Debug Halting Control and Status Register */
 #define CoreDebug_DHCSR_DBGKEY_Pos         16
 #define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)
 #define CoreDebug_DHCSR_S_RESET_ST_Pos     25
 #define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)
 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24
 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)
 #define CoreDebug_DHCSR_S_LOCKUP_Pos       19
 #define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)
 #define CoreDebug_DHCSR_S_SLEEP_Pos        18
 #define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)
 #define CoreDebug_DHCSR_S_HALT_Pos         17
 #define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)
 #define CoreDebug_DHCSR_S_REGRDY_Pos       16
 #define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)
 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5
 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)
 #define CoreDebug_DHCSR_C_MASKINTS_Pos      3
 #define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)
 #define CoreDebug_DHCSR_C_STEP_Pos          2
 #define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)
 #define CoreDebug_DHCSR_C_HALT_Pos          1
 #define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)
 #define CoreDebug_DHCSR_C_DEBUGEN_Pos       0
 #define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)
 /* Debug Core Register Selector Register */
 #define CoreDebug_DCRSR_REGWnR_Pos         16
 #define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)
 #define CoreDebug_DCRSR_REGSEL_Pos          0
 #define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)
 /* Debug Exception and Monitor Control Register */
 #define CoreDebug_DEMCR_TRCENA_Pos         24
 #define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)
 #define CoreDebug_DEMCR_MON_REQ_Pos        19
 #define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)
 #define CoreDebug_DEMCR_MON_STEP_Pos       18
 #define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)
 #define CoreDebug_DEMCR_MON_PEND_Pos       17
 #define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)
 #define CoreDebug_DEMCR_MON_EN_Pos         16
 #define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)
 #define CoreDebug_DEMCR_VC_HARDERR_Pos     10
 #define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)
 #define CoreDebug_DEMCR_VC_INTERR_Pos       9
 #define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)
 #define CoreDebug_DEMCR_VC_BUSERR_Pos       8
 #define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)
 #define CoreDebug_DEMCR_VC_STATERR_Pos      7
 #define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)
 #define CoreDebug_DEMCR_VC_CHKERR_Pos       6
 #define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)
 #define CoreDebug_DEMCR_VC_NOCPERR_Pos      5
 #define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)
 #define CoreDebug_DEMCR_VC_MMERR_Pos        4
 #define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)
 #define CoreDebug_DEMCR_VC_CORERESET_Pos    0
 #define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)

 /* Memory mapping of Cortex-M3 Hardware */
 #define SCS_BASE            (0xE000E000UL)
 #define ITM_BASE            (0xE0000000UL)
 #define CoreDebug_BASE      (0xE000EDF0UL)
 #define SysTick_BASE        (SCS_BASE +  0x0010UL)
 #define NVIC_BASE           (SCS_BASE +  0x0100UL)
 #define SCB_BASE            (SCS_BASE +  0x0D00UL)
 #define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )
 #define SCB                 ((SCB_Type       *)     SCB_BASE      )
 #define SysTick             ((SysTick_Type   *)     SysTick_BASE  )
 #define NVIC                ((NVIC_Type      *)     NVIC_BASE     )
 #define ITM                 ((ITM_Type       *)     ITM_BASE      )
 #define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)
 #if (__MPU_PRESENT == 1)
   #define MPU_BASE          (SCS_BASE +  0x0D90UL)
   #define MPU               ((MPU_Type       *)     MPU_BASE      )
 #endif

 /*******************************************************************************
  *                Hardware Abstraction Layer
  ******************************************************************************/
 /* ##########################   NVIC functions  #################################### */
 static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
 {
   uint32_t reg_value;
   uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */

   reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
   reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
   reg_value  =  (reg_value                                 |
                 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
                 (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
   SCB->AIRCR =  reg_value;
 }


 static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
 {
   return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
 }


 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
 {
   NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
 }


 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
 {
   NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
 }


 static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
 {
   return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
 }


 static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
 {
   NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
 }


 static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
 {
   NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
 }


 static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
 {
   return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
 }


 static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
 {
   if(IRQn < 0) {
     SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
   else {
     NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
 }


 static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
 {

   if(IRQn < 0) {
     return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
   else {
     return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
 }


 static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
 {
   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;

   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

   return (
            ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
            ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
          );
 }


 static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
 {
   uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
   uint32_t PreemptPriorityBits;
   uint32_t SubPriorityBits;

   PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
   SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;

   *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
   *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
 }


 static __INLINE void NVIC_SystemReset(void)
 {
   __DSB();                                                     /* Ensure all outstanding memory accesses included
                                                                   buffered write are completed before reset */
   SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
                  (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
                  SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
   __DSB();                                                     /* Ensure completion of memory access */
   while(1);                                                    /* wait until reset */
 }

 /* ##################################    SysTick function  ############################################ */
 #if (__Vendor_SysTickConfig == 0)

 static __INLINE uint32_t SysTick_Config(uint32_t ticks)
 {
   if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */

   SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
   NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
   SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
   SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
                    SysTick_CTRL_TICKINT_Msk   |
                    SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
   return (0);                                                  /* Function successful */
 }

 #endif

 /* ##################################### Debug In/Output function ########################################### */
 extern volatile int32_t ITM_RxBuffer;
 #define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5
 static __INLINE uint32_t ITM_SendChar (uint32_t ch)
 {
   if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
       (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
       (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
   {
     while (ITM->PORT[0].u32 == 0);
     ITM->PORT[0].u8 = (uint8_t) ch;
   }
   return (ch);
 }


 static __INLINE int32_t ITM_ReceiveChar (void) {
   int32_t ch = -1;                           /* no character available */

   if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
     ch = ITM_RxBuffer;
     ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
   }

   return (ch);
 }


 static __INLINE int32_t ITM_CheckChar (void) {

   if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
     return (0);                                 /* no character available */
   } else {
     return (1);                                 /*    character available */
   }
 }

 #endif /* __CORE_CM3_H_DEPENDANT */

 #endif /* __CMSIS_GENERIC */

 #ifdef __cplusplus
 }
 #endif
CoreDebug_Type::DEMCR
__IO uint32_t DEMCR
Definition: core_cm3.h:757

NVIC_Type::STIR
__O uint32_t STIR
Definition: core_cm3.h:288

SCB_AIRCR_PRIGROUP_Msk
#define SCB_AIRCR_PRIGROUP_Msk
Definition: core_cm3.h:401

CoreDebug_Type::DCRDR
__IO uint32_t DCRDR
Definition: core_cm3.h:756

SCB_Type::DFR
__I uint32_t DFR
Definition: core_cm3.h:323

ITM_Type::u8
__O uint8_t u8
Definition: core_cm3.h:622

SCnSCB_Type
Structure type to access the System Control and ID Register not in the SCB.
Definition: core_cm3.h:531

SCB_Type::AFSR
__IO uint32_t AFSR
Definition: core_cm3.h:321

CoreDebug_Type::DHCSR
__IO uint32_t DHCSR
Definition: core_cm3.h:754

ISR
#define ISR(func)
Define service routine.
Definition: interrupt_sam_nvic.h:65

SCB_Type::ADR
__I uint32_t ADR
Definition: core_cm3.h:324

CoreDebug_Type::DCRSR
__O uint32_t DCRSR
Definition: core_cm3.h:755

SysTick_CTRL_TICKINT_Msk
#define SysTick_CTRL_TICKINT_Msk
Definition: core_cm3.h:584

SCB_Type::HFSR
__IO uint32_t HFSR
Definition: core_cm3.h:317

APSR_Type
Union type to access the Application Program Status Register (APSR).
Definition: core_cm0.h:182

IRQn
IRQn
Definition: ARMCM0.h:35

SysTick_IRQn
Definition: ARMCM0.h:46

SysTick_Type
Structure type to access the System Timer (SysTick).
Definition: core_cm0.h:397

ITM_Type
Structure type to access the Instrumentation Trace Macrocell Register (ITM).
Definition: core_cm3.h:618

NVIC
#define NVIC
Definition: core_cm3.h:862

SCB_Type::DFSR
__IO uint32_t DFSR
Definition: core_cm3.h:318

ITM_Type::u32
__O uint32_t u32
Definition: core_cm3.h:624

SCB_Type::CFSR
__IO uint32_t CFSR
Definition: core_cm3.h:316

SCB_Type
Structure type to access the System Control Block (SCB).
Definition: core_cm0.h:292

SysTick
#define SysTick
Definition: core_cm3.h:861

ITM_Type::TCR
__IO uint32_t TCR
Definition: core_cm3.h:631

SCB
#define SCB
Definition: core_cm3.h:860

ITM_TCR_ITMENA_Msk
#define ITM_TCR_ITMENA_Msk
Definition: core_cm3.h:664

ITM_RXBUFFER_EMPTY
#define ITM_RXBUFFER_EMPTY
Definition: core_cm3.h:1173

SCB_Type::BFAR
__IO uint32_t BFAR
Definition: core_cm3.h:320

SCB_AIRCR_SYSRESETREQ_Msk
#define SCB_AIRCR_SYSRESETREQ_Msk
Definition: core_cm3.h:404

CONTROL_Type
Union type to access the Control Registers (CONTROL).
Definition: core_cm0.h:244

ITM_RxBuffer
volatile int32_t ITM_RxBuffer

SysTick_CTRL_ENABLE_Msk
#define SysTick_CTRL_ENABLE_Msk
Definition: core_cm3.h:587

SysTick_CTRL_CLKSOURCE_Msk
#define SysTick_CTRL_CLKSOURCE_Msk
Definition: core_cm3.h:581

__IO
#define __IO
Definition: core_cm3.h:162

SCB_AIRCR_PRIGROUP_Pos
#define SCB_AIRCR_PRIGROUP_Pos
Definition: core_cm3.h:400

IPSR_Type
Union type to access the Interrupt Program Status Register (IPSR).
Definition: core_cm0.h:205

SCnSCB_Type::ICTR
__I uint32_t ICTR
Definition: core_cm3.h:534

__O
#define __O
Definition: core_cm3.h:161

__I
#define __I
Definition: core_cm3.h:159

ITM_Type::TPR
__IO uint32_t TPR
Definition: core_cm3.h:629

__NVIC_PRIO_BITS
#define __NVIC_PRIO_BITS
Definition: ARMCM0.h:62

NVIC_Type
Structure type to access the Nested Vectored Interrupt Controller (NVIC).
Definition: core_cm0.h:267

CoreDebug_Type
Structure type to access the Core Debug Register (CoreDebug).
Definition: core_cm3.h:752

core_cmInstr.h
CMSIS Cortex-M Core Instruction Access Header File.

CoreDebug
#define CoreDebug
Definition: core_cm3.h:864

SCB_Type::MMFAR
__IO uint32_t MMFAR
Definition: core_cm3.h:319

SCB_AIRCR_VECTKEY_Pos
#define SCB_AIRCR_VECTKEY_Pos
Definition: core_cm3.h:391

SysTick_LOAD_RELOAD_Msk
#define SysTick_LOAD_RELOAD_Msk
Definition: core_cm3.h:591

xPSR_Type
Union type to access the Special-Purpose Program Status Registers (xPSR).
Definition: core_cm0.h:218

SCB_AIRCR_VECTKEY_Msk
#define SCB_AIRCR_VECTKEY_Msk
Definition: core_cm3.h:392

SCB_Type::CPACR
__IO uint32_t CPACR
Definition: core_cm3.h:328

CoreDebug_DEMCR_TRCENA_Msk
#define CoreDebug_DEMCR_TRCENA_Msk
Definition: core_cm3.h:806

ITM_Type::u16
__O uint16_t u16
Definition: core_cm3.h:623

SCB_Type::VTOR
__IO uint32_t VTOR
Definition: core_cm3.h:310

ITM_Type::TER
__IO uint32_t TER
Definition: core_cm3.h:627

core_cmFunc.h
CMSIS Cortex-M Core Function Access Header File.

ITM
#define ITM
Definition: core_cm3.h:863